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  1. #1
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    Need help creating Vivado Timing Constraint

    Hello all,

    Situation is a follows.
    Design in Vivado 2018.4
    Have multiple signals going from clock domain A to clock domain B. I have created a synchronising FF to handle these signals. Furthermore I've created an entity that structurally instantiates the collection of sync'ing FF required to {clock domain crossing (CDC) or cross clocking domain (CCD)}.

    Vivado has reported the following - inter-clock path failures. INTERESTING the reported inter-clock paths is an incomplete list. I have no doubt vivado will add more warnings after I've fixed only some of the startpoint/endpoints.

    Now I have two options either set_max_delay or set_clock_groups -ascyn. Please inform me if I have more. [I never used set_multicycle_path etc].

    The problem I'm having is the following.
    1. I could explicitly go through and create a startpoint to endpoint constraint
    Code:
    set_max_delay -from [get_pins {b_comms.u_comms/u_pcie1/u_sync_pcie/sync_addr/G1.sig_a_int_reg[0]/C}] -to [get_pins {b_comms.u_comms/u_pcie1/u_sync_pcie/sync_addr/sig_b_int_reg[0][0]/D}] 8.0
    2. I could set a constraint based on the clock domain x to clock domain y.
    Code:
    set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins b_comms.u_comms/u_pcie1/u_pcie/inst/pcie3_ip_i/U0/gt_top_i/phy_clk_i/bufg_gt_userclk/O]] -to [get_clocks -of_objects [get_pins b_system_clocks.u_sys_clocks/G_clk.clk_tree_inst/inst/mmcme3_adv_inst/CLKOUT0]] 8.0
    The problem with 1. is that its' tedious. The problem with 2. is that it creates a filter that could ignore signals that I forgot to place into FF-sync.

    Therefore I have experimented with Vivados commands to "TRY" filter a result that is more specific.

    Using the following
    Code:
    get_pins -of_objects [get_cells b_comms.u_comms/u_pcie1/u_sync_pcie]
    I can get a dump of the pins used in the entity
    Code:
     
    b_comms.u_comms/u_pcie1/u_sync_pcie/CLK b_comms.u_comms/u_pcie1/u_sync_pcie/D[0] b_comms.u_comms/u_pcie1/u_sync_pcie/D[10] ...
    Using the following
    Code:
    get_clocks -of_objects [get_cells b_comms.u_comms/u_pcie1/u_sync_pcie]
    I can get a dump of the clocks used in the entity
    Code:
    axi_aclk clk_125m8d8_clk_tree
    Now the crux of the problem, I cannot -do not know how to- filter the pins for a specific clock. Report_property xxx_pin/D will return a table but not specify what clock domain it belongs to.

    Concluding the question
    I would like to
    set max delay -from all pins of clock type axi_aclk located in cell(read entity) sync_pcie -to all pins of clock type clk_125... located in cell(read entity) sync_pcie
    and vice a versa.

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  2. #2
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    Re: Need help creating Vivado Timing Constraint

    Try:
    Code:
    set_false_path -to [get_pins -hier sig_b_int_reg[0][0]/D]
    The name after "-hier" should be written so it hits the register with the asyncronous input in all syncronizers, which means that you only need one contraint for the whole design.
    You should probably add attributes "async_reg" and "dont_touch" to the syncronizer registers (sig_b_int_reg).



  3. #3
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    Re: Need help creating Vivado Timing Constraint

    Have you tried
    Code:
    get_pins -of_objects [your clock here] -filter [NAME =~  "b_comms.u_comms/u_pcie1/u_sync_pcie/*"]
    This will return all pins from a specific clock domain in the given instance.



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  4. #4
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    Re: Need help creating Vivado Timing Constraint

    The "simple" option is to make the clock groups async. This has the effect of making any connections between the two clocks as false paths. But false paths are no longer prefered for CDCs. Ideally, you set a max delay of 2x the faster clock to prevent the path begin too long.

    In addition, its good practice to tag any regs that cross the clock boundary with the "ASYNC_REG" attribute. This should force the fitter to place the registers in the same slice giving a minimal path length.

    Dont be afraid to use the switches and wildcards with paths on set_max delay. There is no need to specify it for every path - its quite nornmal just to use a -to and let the tool find all the paths.

    eg:
    Code:
    set_max_delay -to [get_pins {top/inst*/some_*_inst/areset_reg/D}] [expr 2*$faster_clk]
    And finally, these kind of constraints are not really needed for synthesis. CDCs and pins can usually just be used in implementation. For this, create a "common" xdc file that applies to everything containing clocks etc, and an implementation only xdc. Add them both to the project, and set it only used during implementation:

    Code:
    set_property USED_IN_SYNTHESIS      true [get_files $timing_common_xdc]
    set_property USED_IN_IMPLEMENTATION true [get_files $timing_common_xdc]
    
    set_property USED_IN_SYNTHESIS      false [get_files $impl_only_timing]
    set_property USED_IN_IMPLEMENTATION true [get_files $impl_only_timing]
    And another fun thing - you can use tcl script in your XDC files if you set them to unmanaged:

    Code:
    read_xdc -unmanaged $impl_only_timing

    so you could do constraints based on design conditions and put debug into your XDC files:

    Code TCL - [expand]
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    set DESIGN_ID 0x[format %x $build_id]
    puts "Design id:    $DESIGN_ID"
     
    if {[regexp {0x(?:8|9|c)} $DESIGN_ID]} {
        set_max_delay -to [get_pins {top/inst*/some_*_inst/areset_reg/D}] [expr 2*$faster_clk]
    else {
        set_max_delay -to [get_pins {top/inst*/some_*_inst/areset_reg/D}] [expr 2*$some_other_clk]
    }

    Happy SDCing (its very tedious)



  5. #5
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    Re: Need help creating Vivado Timing Constraint

    What I've discovered -

    Easiest solution to overcome my problem on a Xilinx device is to instantiate a xpm block - xpm_cdc_single/xpm_cdc_array_single.

    However when trying to be clever/unnecessarily complex. I've looked at
    a_scoped_xdc file and
    dynamic_period constraint

    Such that
    ff_sync_cdc.xdc
    Code:
    set a_period [get_property PERIOD [get_clocks -of_objects [get_nets clk_a]]]
    set b_period [get_property PERIOD [get_clocks -of_objects [get_nets clk_b]]]
    set_max_delay -from [get_nets sig_a*] -to [get_nets sig_b*] -datapath_only $b_period
    Then I set the xdc to be linked to ff_sync entity with set_property SCOPED_TO_REF <name_of_module> [get_files <name_of_XDC_file>]

    Problems I'm getting now are related the failure to interpret line "set_max_delay -from [get_nets sig_a*] -to [get_nets sig_b*] -datapath_only $b_period"


    Any suggestions would be appreciated



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  6. #6
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    Re: Need help creating Vivado Timing Constraint

    The best way to get this is to mess about in the TCL conside. start from the get_nets command and ensure it returns a list of nets you expect. Then work backwards.



  7. #7
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    Re: Need help creating Vivado Timing Constraint

    Quote Originally Posted by wesleytaylor View Post
    Code:
    set_max_delay -from [get_nets sig_a*] -to [get_nets sig_b*] -datapath_only $b_period
    Without "-hier" you must match the whole path, and the '*' doesn't match the hierarchy separator '/'.
    I also think that you don't need the "-from" part if the "-to" part only matches your synchronizer registers.
    Try these (not tested by me):
    Code:
    set_max_delay -to [get_nets -hier sig_b*] -datapath_only $b_period
    set_max_delay -from [get_nets -hier sig_a*] -to [get_nets -hier sig_b*] -datapath_only $b_period



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