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[SOLVED] Suppressing the spacing in $fwrite command of Verilog

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tahirsengine

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Hi,

Please see the code below:

Code:
$fwrite(WglFile, "\tFREFH     := input[%dnS:S];", wgl_t_timeplate_FREFH, "\n");

here wgl_t_timeplate_FREFH is of integer type.

When I run this line, the output is like :

Code:
FREFH     := input[          0nS:S];

Please notice the space between bracket start and 0nS. This has to do with the data type of wgl_t_timeplate_FREFH. Is there any way I can suppress this spacing in output.
 

Review System Verilog language reference, paragraph 21.2.1.3 Size of displayed data.

It's regular C format specifier syntax, by the way.
 
Try %0d
Look up any C or Verilog formatting on the web.

That worked. Just mentioning here for the future reference of others.
@FvM The reference that you gave is the reference that explains what is printing with minimum size. Thanks.
 

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