Converting verilog code into a symbol during AMS simulation

[Chinmaye]

Dear all,
I have a verilog code with input in[3:0] and output out[3:0]. When i try to create a symbol for it for ams simulation, it gives me only 2 pins. One pin for input, in<3:0> instead of 4 pins as in[3], in[2], in[1], in[0]. The other is for output, out<3:0> instead of 4 pins. I am really not sure of how to give the inputs to this? AM i missing out on something? Can some one help?

[pancho_hideboo]

Simply they are bus pins.

[Chinmaye]

How will i be able to split the pins? As in, I would like to have 4 pins by name in[0], in[1], in[2], in[3] instead of one pin in[3:0].

[pancho_hideboo]

Simply edit manually.

[Puppet123]

https://community.cadence.com/cadenc...s-in-schematic

[Chinmaye]

Thanks for the help,
So i split the inputs while defining input output pins in the module. For example
module inve(in[1], in[2], out[2], out[1]);
This seems to work