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  1. #1
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    AMS simulation of D-FF

    Hello all,
    I am unable to simulate D-flipflop properly in AMS. The input that i am giving is itself shown incorrect on the wave form window. I was able to simulate simple gates but find ing problems with D flip flop. Attaching the code and waveform.

    Code:
    module DFF_VERI(D,clk,Q);
    input D; // Data input 
    input clk; // clock input 
    output reg Q; // output Q 
    always @(posedge clk) 
    begin
     Q = D; 
    end 
    
    endmodule

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  2. #2
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    Re: AMS simulation of D-FF

    There's no clock signal fed to your circuit, respectively output is uninitialized..

    Confusingly you are providing a multi level ("electrical") signal to the D input which makes no sense for a D-FF.



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  3. #3
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    Re: AMS simulation of D-FF

    The module has no reset and no special-case initialization code,
    so there will be some problems getting an initial solution.


    Here's code for a well-used veriloga DFF from a CMOS standard
    cell library:


    Code Verilog - [expand]
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    // VerilogA for dffr
    // active-low reset, positive-edge clock
     
    `include "constants.h"
    `include "discipline.h"
     
    module dffr ( data, reset, clk, vdd, vss, q);
    input data,reset,clk,vdd,vss;
    output q;
    voltage data, reset, clk, vdd, vss, q;
    real vth, qx;
    integer logicd, logicr;
     
    analog begin
     
      vth=(V(vdd)+V(vss))*0.5;
      logicr = V(reset) > vth;
      @ (cross(V(clk) - vth,1)) logicd = V(data) > vth;
      logicd = logicd * logicr;
      qx=(logicd) ? V(vdd) : V(vss);
      
     
      V(q) <+ transition(qx,1.5n,200p,200p);
     
    end
    endmodule
    Last edited by BradtheRad; 17th September 2019 at 02:40. Reason: Added code formatted window


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