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    Gate Level Simulation

    Do we use .lib for gate level simulation of netlists?

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    Re: Gate Level Simulation

    Quote Originally Posted by fragnen View Post
    Do we use .lib for gate level simulation of netlists?
    Hi,

    Gate level simulation of what netlist? Where? With what?

    You need to give details.
    -------------
    --Akanimo.



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    Re: Gate Level Simulation

    Quote Originally Posted by Akanimo View Post
    Hi,

    Gate level simulation of what netlist? Where? With what?

    You need to give details.
    Are not gate level simulation always done on netlists?

    The post was raised for gate level simulation on netlists.

    Regards



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    Re: Gate Level Simulation

    Quote Originally Posted by fragnen View Post
    Are not gate level simulation always done on netlists?
    The post was raised for gate level simulation on netlists.
    No one can understand what you mean.
    Express in detail with correct terminology.

    Do you mean Gate-Level-HDL which is synthesized from RTL-HDL ?



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    Re: Gate Level Simulation

    Quote Originally Posted by pancho_hideboo View Post
    No one can understand what you mean.
    Express in detail with correct terminology.

    Do you mean Gate-Level-HDL which is synthesized from RTL-HDL ?
    After rtls are synthesized using a synthesis tool like Design Compiler of Synopsys, we get a netlist. The simulation of this netlist is called gate level simulation. Is it clear now?
    Last edited by fragnen; 18th September 2019 at 07:48.



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    Re: Gate Level Simulation

    Quote Originally Posted by fragnen View Post
    After rtls are synthesized using a synthesis tool like Design Compiler of Synopsys, we get a netlist. The simulation of this netlist is called gate level simulation. Is it clear now?
    Yes. You need an SDF file to be simulated with the netlist. That's all.
    Really, I am not Sam.



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    Re: Gate Level Simulation

    Quote Originally Posted by fragnen View Post
    we get a netlist.
    It is Gate-Level-HDL.

    Quote Originally Posted by ThisIsNotSam View Post
    You need an SDF file to be simulated with the netlist.
    I don’t think he reaches to SDF annotation.

    Simply his purpose requires standard cell library or technology library.
    Last edited by pancho_hideboo; 18th September 2019 at 11:34.



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    Re: Gate Level Simulation

    Quote Originally Posted by pancho_hideboo View Post
    It is Gate-Level-HDL.

    I don’t think he reaches to SDF annotation.

    Simply his purpose requires standard cell library or technology library.
    at a bare minimum, a verilog file of the standard cell library is needed. this should be combined with an SDF, otherwise you get some timing model that is not realistics like a unit delay model (ie, every cells takes 1 time unit to compute its output).
    Really, I am not Sam.



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    Re: Gate Level Simulation

    Quote Originally Posted by ThisIsNotSam View Post
    at a bare minimum, a verilog file of the standard cell library is needed. this should be combined with an SDF, otherwise you get some timing model that is not realistics like a unit delay model (ie, every cells takes 1 time unit to compute its output).
    Can a .lib files of a standard cells be used instead of a verilog models of standard cell for gate level simulation?



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    Re: Gate Level Simulation

    Quote Originally Posted by fragnen View Post
    Can a .lib files of a standard cells be used instead of a verilog models of standard cell for gate level simulation?
    in theory, yes. lib files do contain the equation of the cell. in practice, no, no simulator that I know of will take a .lib as input
    Really, I am not Sam.



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    Re: Gate Level Simulation

    Quote Originally Posted by ThisIsNotSam View Post
    in theory, yes. lib files do contain the equation of the cell. in practice, no, no simulator that I know of will take a .lib as input
    But the equation in .lib may not be similar to the model file. For example if a D-fliplop is taken its behavioural code is understood as a D-flipflop but the equation of it does not reflect the behaviour of a D-flipflop. A LEC tool can read those equations of cells in a .lib if I am not doing any mistake.



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    Re: Gate Level Simulation

    Quote Originally Posted by fragnen View Post
    But the equation in .lib may not be similar to the model file. For example if a D-fliplop is taken its behavioural code is understood as a D-flipflop but the equation of it does not reflect the behaviour of a D-flipflop. A LEC tool can read those equations of cells in a .lib if I am not doing any mistake.
    what do you want me to say? if you try to hack a solution, you get as far as the hack takes you. there are standard ways of doing things, stick to those and you will not have to worry about model incoherence.
    Really, I am not Sam.



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