Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Alternative of “can not set both range and type on function declaration” in verilog?

Status
Not open for further replies.
D

daskk62

Guest
I am writing a verilog code for calculation of variance, in my verilog code I am calling a definition file, the definition file is as follows
`define MAXIMUM_FUNC_WIDTH 64

function integer clog2(input reg [`MAXIMUM_FUNC_WIDTH-1:0] value);
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction

function reg [`MAXIMUM_FUNC_WIDTH-1:0] pow(input integer base, input integer index);
begin
for (pow=1; index>=0; pow=pow*base)
index = index - 1;
end
endfunction
but in the line function reg [MAXIMUM_FUNC_WIDTH-1:0] pow(input integer base, input integer index); it is showing error like can not set both range and type on function declaration. In think this is related to system verilog. But how can I use the same line for verilog only. What will be the modefication?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top