natalfra
Newbie level 4
Hi everyone, I have some problems with the VHDL code of INPUT CAPTURE and OUTPUT COMPARE.
I did the architecture (logical components) of this two modes but I don't know how to describe them in a simple VHDL code.
Can someone help me, please?
Thanks
I did the architecture (logical components) of this two modes but I don't know how to describe them in a simple VHDL code.
Can someone help me, please?
Thanks