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    [moved] VHDL of input capture and output compare

    Hi everyone, I have some problems with the VHDL code of INPUT CAPTURE and OUTPUT COMPARE.

    I did the architecture (logical components) of this two modes but I don't know how to describe them in a simple VHDL code.

    Can someone help me, please?

    Thanks

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    Re: [moved] VHDL of input capture and output compare

    These are the two schemes.Click image for larger version. 

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    Re: [moved] VHDL of input capture and output compare

    You question isn't clear.
    What do you mean by input capture and output compare?

    If you already have an architecture diagram post it so we have an idea what you are trying to do.

    If you just mean a register and a compare then...
    Code VHDL - [expand]
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    -- register (for capturing)
    process (clk)
    begin
      if (capture_input = '1') then
        capture_reg <= input_data;
      end if;
    end process;

    Code VHDL - [expand]
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    -- a compare
    process (a, b)
    begin
      if (a = b) then
        is_equal <= '1';
      else
        is_equal <= '0'
      end if;
    end process;

    Both of these are simple VHDL constructs, which can be found on any VHDL tutorial site. You should probably visit one of those sites to learn some VHDL before tackling this project.

    - - - Updated - - -

    Ugh, gated clocks, you should not use gated clocks in an FPGA you'll probably never get the design to work reliably. Make a synchronous design using a single higher speed clock instead of generating a bunch of "clocks" from random signals. You will have more success with the implementation tools for FPGAs if you make a synchronous design.


    1 members found this post helpful.

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    Re: [moved] VHDL of input capture and output compare

    The problem is that the test of the homework is to describe in VHDL code the scheme that I sent to you!



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    Re: [moved] VHDL of input capture and output compare

    Theres your answer - it is homework. So you should be researching how to write VHDL, not expecting someone to do it for you.



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    Re: [moved] VHDL of input capture and output compare

    I searched all the day but I really don't know how to do it, this is the reason why I wrote here, for some help.

    I hope that someone will help me.



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    Re: [moved] VHDL of input capture and output compare

    There are many VHDL tutorials on the web.



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    Re: [moved] VHDL of input capture and output compare

    Yes, i know. It's very important for me to receive some suggestions about this 2 codes.

    As I said one hour ago, I hope that someone will help me.



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    Re: [moved] VHDL of input capture and output compare

    Quote Originally Posted by natalfra View Post
    I searched all the day but I really don't know how to do it, this is the reason why I wrote here, for some help.

    I hope that someone will help me.
    ASIC world has a bunch of examples of various blocks that are used to create larger designs.
    http://www.asic-world.com/examples/vhdl/index.html

    If you can't translate from the blocks in your block diagram to the actual circuits that are required then I see no point in helping further as what you really need help with is learning basic digital design.



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