+ Post New Thread
Results 1 to 8 of 8
  1. #1
    Member level 5
    Points: 1,077, Level: 7

    Join Date
    Jan 2016
    Posts
    82
    Helped
    0 / 0
    Points
    1,077
    Level
    7

    Verilog-a code to latch analog voltages

    Dear all,
    I am trying to model analog latch in verilog-a but have been unable to do it. The requirement is as follows
    It is required to sample an analog value at positive clock cycle of CLK2 and hold the same value even during the negative clock cycle of CLK2.
    Any leads??

    •   AltAdvertisement

        
       

  2. #2
    Advanced Member level 5
    Points: 16,969, Level: 31
    pancho_hideboo's Avatar
    Join Date
    Oct 2006
    Location
    Real Homeless
    Posts
    2,610
    Helped
    698 / 698
    Points
    16,969
    Level
    31

    Re: Verilog-a code to latch analog voltages

    Use @cross().



    •   AltAdvertisement

        
       

  3. #3
    Member level 5
    Points: 1,077, Level: 7

    Join Date
    Jan 2016
    Posts
    82
    Helped
    0 / 0
    Points
    1,077
    Level
    7

    Re: Verilog-a code to latch analog voltages

    @cross() does not allow V() inside it. Hence it cannot be used



    •   AltAdvertisement

        
       

  4. #4
    Advanced Member level 5
    Points: 16,969, Level: 31
    pancho_hideboo's Avatar
    Join Date
    Oct 2006
    Location
    Real Homeless
    Posts
    2,610
    Helped
    698 / 698
    Points
    16,969
    Level
    31

    Re: Verilog-a code to latch analog voltages

    Quote Originally Posted by Chinmaye View Post
    @cross() does not allow V() inside it.
    Hence it cannot be used
    No.
    You can not understand Verilog-A at all.

    if V(clk2) >=0 aho = V(in);
    @cross(V(clk2), -1) aho = V(in);
    V(out) <+ aho;
    Last edited by pancho_hideboo; 11th September 2019 at 18:59.


    1 members found this post helpful.

  5. #5
    Advanced Member level 5
    Points: 39,692, Level: 48

    Join Date
    Mar 2008
    Location
    USA
    Posts
    6,412
    Helped
    1871 / 1871
    Points
    39,692
    Level
    48

    Re: Verilog-a code to latch analog voltages




    •   AltAdvertisement

        
       

  6. #6
    Full Member level 4
    Points: 1,398, Level: 8

    Join Date
    Jan 2019
    Location
    Belgium
    Posts
    199
    Helped
    83 / 83
    Points
    1,398
    Level
    8

    Re: Verilog-a code to latch analog voltages

    Quote Originally Posted by Chinmaye View Post
    Dear all,
    I am trying to model analog latch in verilog-a but have been unable to do it. The requirement is as follows
    It is required to sample an analog value at positive clock cycle of CLK2 and hold the same value even during the negative clock cycle of CLK2.
    Any leads??
    Look at page 113 of http://www.lumerink.com/docs/VerilogA.pdf

    Your exact solution is given!!



  7. #7
    Advanced Member level 5
    Points: 16,969, Level: 31
    pancho_hideboo's Avatar
    Join Date
    Oct 2006
    Location
    Real Homeless
    Posts
    2,610
    Helped
    698 / 698
    Points
    16,969
    Level
    31

    Re: Verilog-a code to latch analog voltages

    Quote Originally Posted by vivekroy View Post
    Look at page 113 of http://www.lumerink.com/docs/VerilogA.pdf
    Your exact solution is given!!
    This is not transparent latch.

    For V(Clk2)=High, V(out)=V(in) ; Tranparent
    Then V(in) is captured at negative edge of V(Clk2).
    V(out) is constant during V(Clk2)=Low ; Hold Mode.


    1 members found this post helpful.

  8. #8
    Full Member level 4
    Points: 1,398, Level: 8

    Join Date
    Jan 2019
    Location
    Belgium
    Posts
    199
    Helped
    83 / 83
    Points
    1,398
    Level
    8

    Re: Verilog-a code to latch analog voltages

    Here you go

    Code:
    // VerilogA code
    
    `include "constants.vams"
    `include "disciplines.vams"
    
    module veriloga_latch(vin,vclk,vout_sampled);
    input vin,vclk;
    output vout_sampled;
    voltage vin, vclk, vout_sampled;
    parameter real vdd=1;
    real vsample=0;
    analog begin
    	if (V(vclk)>0.9*vdd) begin
    		vsample=V(vin);
    	end
    	V(vout_sampled) <+ vsample;
    	end
    	
    
    
    endmodule
    Here is the op:
    Click image for larger version. 

Name:	latch_op.JPG 
Views:	1 
Size:	62.3 KB 
ID:	155492


    1 members found this post helpful.

--[[ ]]--