# Verilog-a code to latch analog voltages

1. ## Verilog-a code to latch analog voltages

Dear all,
I am trying to model analog latch in verilog-a but have been unable to do it. The requirement is as follows
It is required to sample an analog value at positive clock cycle of CLK2 and hold the same value even during the negative clock cycle of CLK2.

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2. ## Re: Verilog-a code to latch analog voltages

Use @cross().

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3. ## Re: Verilog-a code to latch analog voltages

@cross() does not allow V() inside it. Hence it cannot be used

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4. ## Re: Verilog-a code to latch analog voltages

Originally Posted by Chinmaye
@cross() does not allow V() inside it.
Hence it cannot be used
No.
You can not understand Verilog-A at all.

if V(clk2) >=0 aho = V(in);
@cross(V(clk2), -1) aho = V(in);
V(out) <+ aho;

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6. ## Re: Verilog-a code to latch analog voltages

Originally Posted by Chinmaye
Dear all,
I am trying to model analog latch in verilog-a but have been unable to do it. The requirement is as follows
It is required to sample an analog value at positive clock cycle of CLK2 and hold the same value even during the negative clock cycle of CLK2.
Look at page 113 of http://www.lumerink.com/docs/VerilogA.pdf

7. ## Re: Verilog-a code to latch analog voltages

Originally Posted by vivekroy
Look at page 113 of http://www.lumerink.com/docs/VerilogA.pdf
This is not transparent latch.

For V(Clk2)=High, V(out)=V(in) ; Tranparent
Then V(in) is captured at negative edge of V(Clk2).
V(out) is constant during V(Clk2)=Low ; Hold Mode.

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8. ## Re: Verilog-a code to latch analog voltages

Here you go

Code:
// VerilogA code

`include "constants.vams"
`include "disciplines.vams"

module veriloga_latch(vin,vclk,vout_sampled);
input vin,vclk;
output vout_sampled;
voltage vin, vclk, vout_sampled;
parameter real vdd=1;
real vsample=0;
analog begin
if (V(vclk)>0.9*vdd) begin
vsample=V(vin);
end
V(vout_sampled) <+ vsample;
end

endmodule
Here is the op:

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