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  1. #1
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    VHDL scope vs visibility vs visibility by selection

    Hello all,

    This following is a derived from my desire to keep a signal declaration local to a specific block, but use it in a different block. I know if I was to move the "scope" of the signal declaration to the architecture I would be able to apply visibility by selection.

    Can a signal local to a specific block ever be used elsewhere? I'm experimenting with visibility by selection.

    See the following. I would like to assign signal b to the a_block.a.

    Code VHDL - [expand]
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    library ieee;
    use ieee.std_logic_1164.all;
     
     
    entity tb is
        end entity tb;
     
     
    architecture ar_tb of tb is
     
        signal a : std_logic_vector(3 downto 0);
     
    begin
     
        process is
        begin
            wait for 1 ns;
            a <= x"0";
            wait for 49 ns;
            a <= x"1";
            wait for 97 ns;
            a <= x"2";
            wait for 17  ns;
            a <= x"3";
            wait for 10 ns;
            wait;
        end process;
     
        a_block : block
     
            signal a : std_logic_vector(3 downto 0);
     
        begin
            
            process(ar_tb.a) is -- , work.ar_tb.b_block.b) is -- , ar_tb.b_block.b)
            begin
                if ar_tb.a'event then
                    a <= ar_tb.a ;
                end if;
                --if ar_tb.b_block.b'event then
                    --a <= ar_tb.b_block.b;
                --end if;
            end process;
     
        end block a_block;
     
        b_block : block
            signal b : std_logic_vector(3 downto 0);
        begin
            process
            begin
                wait for 5 ns;
                b <= X"F";
                wait for 9 ns;
                b <= X"E";
                wait for 99 ns;
                b <= X"9";
                wait;
            end process;
        end block b_block;
        
        process
        begin
            wait for 1 us;
            report "" severity failure;
        end process;
     
    end architecture;

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  2. #2
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    Re: VHDL scope vs visibility vs visibility by selection

    With VHDL 2008, you can use external names. But you can only see inside something thats already in scope. So in your example, you cannot see inside "b_block" from "a_block" because it is declared after a_block. If you moved b_block ahead of a_block, you could write this:

    Code VHDL - [expand]
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    a <= << signal ^.b_block.b : std_logic_vector(3 downto 0) >> ;

    Because of the long syntax, it is normal to create aliases to external items when you need it multiple times:

    Code VHDL - [expand]
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    alias b_block_b is << signal ^.b_block.b : std_logic_vector(3 downto 0) >> ;
    ...
    a <= b_block_b;


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  3. #3
    Full Member level 5
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    Re: VHDL scope vs visibility vs visibility by selection

    Thanks Tricky,

    I was aware that the ^ - equivalent to "cd .." - looks up a level.

    However I'm surprised to see that the order of block declarations matter. Although the statements declared within the architecture are concurrent to each other, it appears that the order matters. I don't know how the scope of b_block is visible by a_block when it's above, but not when below. I'd love to understand. In sw programming they have local & global variables. whereas in the land of firmware hdl - we have scope and visibility.

    Below are two pictures. One from b_block after a_block and one with b_block before a_block.
    Click image for larger version. 

Name:	b_block_after.PNG 
Views:	2 
Size:	8.7 KB 
ID:	155439Click image for larger version. 

Name:	b_block_before.PNG 
Views:	1 
Size:	11.1 KB 
ID:	155440

    Is the scope overflow possible because during the initialisation phase?

    I'm reading "effective coding with vhdl - principles and best practice" by ricardo jasinski. <- so far I think the book is brilliant.

    However going beyond the book I'm trying to understand the scope and visibility within a simulation.
    Given what you said about order. Where does it fail because of order?
    anaylsis -> elaboration > initialisation > signal update | process execution (loop)
    Last edited by wesleytaylor; 10th September 2019 at 15:29.



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  4. #4
    Advanced Member level 5
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    Re: VHDL scope vs visibility vs visibility by selection

    VHDL is a procedural language like any other, with scope the same as any other language. Statements are executed in the order they are written. So during the elaboration, everything is elaborated in order. It elaborates block_a before block_b (because of code order), and hence cannot find the path to B if you try an external name to it.


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