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    Class D amplifier simulation

    Hi all,

    I'm actually playing with LTspice to implement a class D amplifier.

    Below is a capture of the schematic and simulation results. Can someone explain me why I cannot get an oscillation of +/- 15V at R1, instead of +/- 2V on the plotted area?

    Sounds like a newbie question sorry

    Thanks

    Click image for larger version. 

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    Re: Class D amplifier simulation

    Insufficient gate drive voltage for high side transistors. You are applying 5V relative to ground but 5V relative to respective source terminal is required.



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    Re: Class D amplifier simulation

    Quote Originally Posted by FvM View Post
    Insufficient gate drive voltage for high side transistors. You are applying 5V relative to ground but 5V relative to respective source terminal is required.
    Hi Fvm, indeed, high side transistors sources are not connected to ground! I just retried the simulation with higher voltages on high side gates, and it's working.

    Thanks for your help,



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    Re: Class D amplifier simulation

    Common to simulate with an individual source for each gate drive. Unlike real life there is no penalty for fully isolated gate drive in the simulated. Connect the gate drive source across Vgs.



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    Re: Class D amplifier simulation

    I wouldn't even bother using real FET models, at least to start. Just use voltage controlled switches in place of the FETs (if your load is inductive, make sure to put diodes across the switches). Simulation time will be much faster. Later when you want to look at switching behavior in more detail you can drop in FET models.



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    Re: Class D amplifier simulation

    Quote Originally Posted by asdf44 View Post
    Common to simulate with an individual source for each gate drive. Unlike real life there is no penalty for fully isolated gate drive in the simulated. Connect the gate drive source across Vgs.
    This circuit is intended to be implemented in real life. What could be the problems of using same gate source for Mosfet Q1+ Q3? (and Q2+Q4). What do you mean by "Connect the gate drive source across Vgs"?



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    Re: Class D amplifier simulation

    Quote Originally Posted by mtwieg View Post
    I wouldn't even bother using real FET models, at least to start. Just use voltage controlled switches in place of the FETs (if your load is inductive, make sure to put diodes across the switches). Simulation time will be much faster. Later when you want to look at switching behavior in more detail you can drop in FET models.
    Hi, actually the load will be capacitive (piezoelectric transducer). Do you also recommend the use of flywheel diodes?



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    Re: Class D amplifier simulation

    Quote Originally Posted by vrtec View Post
    Hi, actually the load will be capacitive (piezoelectric transducer). Do you also recommend the use of flywheel diodes?
    Well if the load really is just a capacitance, then no the flywheel diodes don't matter.

    Capacitive loads have their own problems though, mainly large current spikes and switching losses. I assume you will actually want to use an LC filter between the FETs and the piezo in order to filter out the ripple. And then the inductance in that filter will necessitate the flywheel diodes again...



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    Re: Class D amplifier simulation

    Quote Originally Posted by mtwieg View Post
    Well if the load really is just a capacitance, then no the flywheel diodes don't matter.

    Capacitive loads have their own problems though, mainly large current spikes and switching losses. I assume you will actually want to use an LC filter between the FETs and the piezo in order to filter out the ripple. And then the inductance in that filter will necessitate the flywheel diodes again...
    You're right, there will be an LC filter at the output! Thanks for the advices!

    Regards,



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