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    Current reference design for CS-DAC

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    Hi All,

    I am designing a reference circuit for the current steering DAC. The current provided is 10 uA and I need a current of 500nA as LSB current. I decided to take up PMOS based DAC with nmos cascode current mirror as its reference (as shown in the figure).

    I was able to achieve the design working untill nmos stage, giving 2uA to Pmos counterpart. When I stack pmos cascode over nmos cascode(highlighted in the figure), the pmos cascode pair in the rail isn't biased. I have mentioned the W/L ratios in the figure.

    1) By simulation I see that most of the Vdd is consumed by nmos cascode transitor (Vds), why ?
    2) How do I properly bias the upper 2 pmos transistors when they are stacked above 2 nmos tranisitors.

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    Re: Current reference design for CS-DAC

    1) I think your wp/wn ratio is too large. Increase your nmos widths, keeping the original w/l ratios.

    2) If you decrease the above widths ratio by this method, you should be able to keep your pmos biasing scheme.



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    Re: Current reference design for CS-DAC

    Quote Originally Posted by erikl View Post
    1) I think your wp/wn ratio is too large. Increase your nmos widths, keeping the original w/l ratios.

    2) If you decrease the above widths ratio by this method, you should be able to keep your pmos biasing scheme.
    The wp/wn ratio is 2, both for cascode and mirror transitor with respect to its nmos counter part. Should I still decrease the ratio or increase ?



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    Re: Current reference design for CS-DAC

    ad 1) if some of transistor consumes almost all Vdd it means, there is no current in this branch and such transistor is probably cuted-off (or guy below).
    ad 2) In your 2µA branches you have (looking from left respectively): diode+DC shifter providing Vds for current sources and diode in other branch. It means that on left branch PMOSes needs at least Vth+2·Vdssat which can be ca 600mV, while on the right Vth+Vdssat so ca 500mV. You can relax it by changing flavor of transistor (lower Vth) or by biasing them in lower inversion region (by increase W/L ratio).

    To ensure proper biasing in such HSCM, ensure enough voltage for current sources (fets on the rails). It mean, that triode biased guys in cascode biasing branches, should has Vds>Vdssat+some margin (this voltage is next copied by cascode biasing as a Vds for current sources). It mean that for moderate inversion it should be ca 120mV in room temperature, while in strong inversion ca 250mV. If you are not sure how to achieve it, start by replacing this triode connected level shifters by dc voltage sources with 150mV dc voltage to ensure at least 150mV of Vds for current sources. When You find good W/L for cascodes and current sources (mean all will be saturated), then change ideal sources on transistor and start with sthing like W/4L of current sources and then trimm this in parametric sweep if needed.

    //edit:
    You can also try to start with ideal current source to achieve reasonable voltage drop on PMOS diodes in these 2µA branches.


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    Re: Current reference design for CS-DAC

    Quote Originally Posted by Dominik Przyborowski View Post
    ad 1) if some of transistor consumes almost all Vdd it means, there is no current in this branch and such transistor is probably cuted-off (or guy below).
    ad 2) In your 2µA branches you have (looking from left respectively): diode+DC shifter providing Vds for current sources and diode in other branch. It means that on left branch PMOSes needs at least Vth+2·Vdssat which can be ca 600mV, while on the right Vth+Vdssat so ca 500mV. You can relax it by changing flavor of transistor (lower Vth) or by biasing them in lower inversion region (by increase W/L ratio).

    To ensure proper biasing in such HSCM, ensure enough voltage for current sources (fets on the rails). It mean, that triode biased guys in cascode biasing branches, should has Vds>Vdssat+some margin (this voltage is next copied by cascode biasing as a Vds for current sources). It mean that for moderate inversion it should be ca 120mV in room temperature, while in strong inversion ca 250mV. If you are not sure how to achieve it, start by replacing this triode connected level shifters by dc voltage sources with 150mV dc voltage to ensure at least 150mV of Vds for current sources. When You find good W/L for cascodes and current sources (mean all will be saturated), then change ideal sources on transistor and start with sthing like W/4L of current sources and then trimm this in parametric sweep if needed.

    //edit:
    You can also try to start with ideal current source to achieve reasonable voltage drop on PMOS diodes in these 2µA branches.
    Hi Dominik,
    Definitely I will try the steps suggested by you.

    a)The biasing transistor for HSCM is 1/4 or 1/5 times to that of current source or cascodes ?
    b) For now, I have kept it 1/10 th (to push it more into saturation) to that of current sources in nmos stage and all transitors seem properly biased., is this fine ?



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  6. #6
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    Re: Current reference design for CS-DAC

    Ad a) start from one number, make parametric sweep to find optimum
    Ad b) don't mix saturation and inversion level. It is not the same.
    Start with W/L=1 for 1uA for nmos and 3 for pmos and look on the current in branches and voltage on transistors.

    It would be helpful if you show schematic with annotated current and voltages


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