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Need of a Verilog code to generate clock signal for 10Mhz with system clock 50Mhz.

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VERILOG CODE to generate clock signal for 10Mhz with system clock 50Mhz
Need Verilog code for generating two signals
1.clock signal to generate 10Mhz
2. at the same time the second signal has to toggle its sate on specific count on "negative" edge period
3. How to call a function after a specific clock period?

here i'm sharing a clock signal generation verilog code of 10Mhz from system clock 50Mhz

Code Verilog - [expand]
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module clk_div(clk,reset, clk_out );
parameter N=5;
parameter R=3;// Detramains number of binary bits to present the value of "N" 
input clk;
input reset;
output clk_out;
 
reg [R-1:0] pos_count, neg_count;
wire [R-1:0] r_nxt;
 
always @(posedge clk)
if (reset)
pos_count <=0;
else if (pos_count ==(N-1))
pos_count <=0;
else 
pos_count<= pos_count +1;
 
always @(negedge clk)
if (reset)
neg_count <=0;
else  if (neg_count ==(N-1)) 
neg_count <=0;
  
else 
neg_count<= neg_count +1;
assign clk_out = ((pos_count == (N-1)) | (neg_count == (N-1)));
endmodule
 
Last edited by a moderator:

Hi,

Take a piece of paper and draw the timing diagram for 50MHz and 10MHz.

Then with 50% duty cycle you will see that the edges of the 10MHz will fall on rising as well as falling edge of the 50MHz.
But usually only the rising edge of the system clock will be used.

Either generate 2:5 duty cycle or use a PLL.

Klaus
 

The logic in post #1 has some issues.
The phase between pos_count and neg_count is undetermined. Depending on the reset timing either pos_count or neg_count will increment first, giving different clk_out waveforms. It's even possible that reset release is coinciding with a clock edge, resulting in unexpected counter values.

You may do this:
1. Use a reset synchronizer (if not already present)
2. Use only one counter, derive the neg_edge action from pos_edge controlled signals.

Be aware that generated clocks are likely to cause timing issues if they are combined with the original clock in downstream logic.
 

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