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    What is the difference between BVDSS and BVDS

    Hi, Which is Drain to source breakdown voltage and substrate breakdown voltage. Can you aslo elaborate what they are exactly.
    Thanks

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    Re: What is the difference between BVDSS and BVDS

    You're surely asking about the model parameter syntax of a specific tool. What is it?



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    Re: What is the difference between BVDSS and BVDS

    Quote Originally Posted by FvM View Post
    You're surely asking about the model parameter syntax of a specific tool. What is it?
    I know, in general, BVDS means drain to source breakdown voltage and I wanted to know how substrate breakdown voltage is represented. While I was in search of that I came across BVDSS, which I don't know about.



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    Re: What is the difference between BVDSS and BVDS

    The last letter of Semiconductor syntax indicates the condition of the third terminal. Which in this case is the gate and is Shorted
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    Re: What is the difference between BVDSS and BVDS

    Quote Originally Posted by schmitt trigger View Post
    The last letter of Semiconductor syntax indicates the condition of the third terminal. Which in this case is the gate and is Shorted
    Thanks. How is substrate breakdown voltage is denoted, any short form? I am looking for its value in the PDK but I find it nowhere.



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    Re: What is the difference between BVDSS and BVDS

    That would be something like BVdb_ but this is often not
    specified separately (especially if the foundry knows that
    lateral punchthrough or hot carrier reliability degradation
    happens well below D-B breakdown, which would be a
    normal device-design-to expectation (why would you let
    the isolation junction be the weak link in process construction?).



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