T
treez
Guest
At an interview today, the engineer told me that Voltage mode controlled SMPS’s need slope compensation to be added when the duty cycle goes >0.5………he said that this slope compensation would take the form of increasing the slope of the already_present synthesized ramp that exists in voltage mode converters….he drew it for me, and his synthesized_ramp was piecewise linear …ie a straight line with slope A, which then “kinked” to a straight line of slope B (>A). So his synthesized ramp was like “dog-legged” kind of thing.
I actually suspect he was bluffing me, would you agree?
He also told me that Voltage mode converters were simpler than current mode converters.
We were talking with reference to a Buck converter, and I pointed out the power stage double pole that exists with voltage mode control, but this left him not impressed.
He also told me how a current sense transformer in a Buck converter would best go downstream of the inductor. He pointed out that where I had placed a CST (upstream of the FET) was an unwise choice.
I actually suspect he was bluffing me, would you agree?
He also told me that Voltage mode converters were simpler than current mode converters.
We were talking with reference to a Buck converter, and I pointed out the power stage double pole that exists with voltage mode control, but this left him not impressed.
He also told me how a current sense transformer in a Buck converter would best go downstream of the inductor. He pointed out that where I had placed a CST (upstream of the FET) was an unwise choice.