Hi,
I have a Systemverilog Script that is generating WGL script for every testcase that I run for simulation using TCL (do files). The issue is, in Modelsim everything is ideal(no delays)). And I think the same will be reflected in generated WGL files, as by inspecting WGL it is clear that in each vector outputs are directly written on the same line(no delays).
As the background of the project, I am working on a project, mainly written in Verilog and I am testing my system using testcases (mainly written in Verilog). This project is an ASIC design project.

So my question is, how to insert delays in WGL files that are anticipated from the end of the design phase? Any document or link that might help?