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CDC - How make merge data after conversion?

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arkadyy

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Hello,

For the first time I deal with crossing clock domains (slow-to-fast) and I have faced a problem.

I recieve constant stream of data, which I have to filter, but before processing data have to move from 100 MHz to 240 MHz domain. I used standard asynchronous FIFO approach and I manage to succesfully partition my data and transfer to new domain. Effects are visiable on attached screen shot. The problem is that when I feed that partitioned data into Xilinx FIR Compiler, my outputs signal turns into garbage.

So, my question is how to merge, partitioned by CDC data to obtain stream like before clock conversion? Maybe there are some methods to do so, which I'm not aware of, I will be glad to learn some new techniques and gain more knowledge. I don't know even how to google it properly.

Best regards,
Arkady

ss.jpg
 
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You're reading at 2.4x of the write rate, so the FIFO goes nearly empty. Apparently you are stopping the reading at the 2.4x rate when almost empty, and restarting at programmable full. During that interval between almost empty and progammable full there is nothing to read from the FIFO as the 100 MHz domain has to refill it. That is why your output FIFO waveform is compressed.

The issue isn't a CDC problem it is the discrepancy in data rates. If you want to run the FIR at 240 MHz then you need to feed it data at 240 MHz. You can always upsample the 100 MHz data to 240 MHz before you send it to the FIR.
 

Like ads-ee said, you need to upsample your data. With your current design FIFO will always empty faster than it is filled. Why not get rid of the FIFO and just use flip-flops to synchronize data from 100 MHz to 240 MHz clock domain?
 

Yes, exactly! Data will be coming constantly in real time, so that was my idea to somehow transfer data to 240 Mhz domain in small chunks. Thank you, I will look into it.
 

Like ads-ee said, you need to upsample your data. With your current design FIFO will always empty faster than it is filled. Why not get rid of the FIFO and just use flip-flops to synchronize data from 100 MHz to 240 MHz clock domain?

According to my knowledge I don't think this is a good idea, due to possible data skew.
 

I receive constant stream of data, which I have to filter, but before processing data have to move from 100 MHz to 240 MHz domain.
Unfortunately, the purpose of the clock rate change wasn't clearly mentioned. Is it up-sampling? Please clarify.
 

The reason behind clock rate change is that data incoming to FPGA with 100 Msps are out of phase with 80 MHz clock, which will be send data out of FPGA. I want to move data into clock domain that is in phase with future 80 MHz and has common divisor with 100 and 80, so I pick up 240 MHz, which also run fir filters. At the and of the day, in DSP block data from ADC will be downsampled to 10 MHz by FIR decimation filters.

clocks.jpg
 

As far as I understood the problem, the data undergoes a 10:1 down sampling. The other involved clock rates are data processing clocks, but not related to sampling rates. The only requirement is that you must be able to transport and process the data without data loss. That's a question of appropriate stream processing.

If you see other sampling rates than 100 and 10 Msps involved, please explain the intended processing scheme more detailed.
 

According to my knowledge I don't think this is a good idea, due to possible data skew.
You will have data skew because 240 MHz is not a multiple of 100 MHz, so for some input samples you will have two output samples and for some you will have three output samples. If you want to upsample so as to have a continuous data stream for the filter, and also want to avoid data skew, then you'll have to do interpolation.
 

As far as I understood the problem, the data undergoes a 10:1 down sampling. The other involved clock rates are data processing clocks, but not related to sampling rates. The only requirement is that you must be able to transport and process the data without data loss. That's a question of appropriate stream processing.

If you see other sampling rates than 100 and 10 Msps involved, please explain the intended processing scheme more detailed.

Thank you for answer, and yes that's the problem, but there are few more requirements. In the future there will be eight DSP modules with 10 MHz output data rate, that's why output interface has to run with 80 Mhz - One data packet contains eight sets of processed data. Data with 10Msps rate have to be align to 80 Mhz clock. Filters in DSP block have to process data as fast as possible, so for now to match 80 Mhz, I choosed 240 Mhz clock.

But in the first place I have to be sure that I feed to system right data with clock, which phase is perfectly align to 80 MHz clock. 100 MHz and 80 Mhz are not in phase so I have to find the way to synchronize 100 Msps input data to match that 80 MHz clock.


You will have data skew because 240 MHz is not a multiple of 100 MHz, so for some input samples you will have two output samples and for some you will have three output samples. If you want to upsample so as to have a continuous data stream for the filter, and also want to avoid data skew, then you'll have to do interpolation.

That's right, I want to avoid that random two or three output samples situation.
 

100 MHz and 80 Mhz are not in phase so I have to find the way to synchronize 100 Msps input data to match that 80 MHz clock.
The asynchronous FIFO does the synchronisation. After transfering the data to 240 MHz domain (or whatever clock rate >= 100 MHz you are using), you do the filtering and downsampling with a multirate FIR.

Using a 240 MHz doesn't seem strictly necessary. You can also decimate in the 100 MHz domain and transfer the 10 MHz stream to 80 MHz domain by asynchronous FIFO.
 

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