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  1. #1
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    Charge pump topology

    Hi everyone,

    I have a task to design a charge pump to generated a output voltage of 3.3 V from 0.8 V supply with load current of 8 mA in 22nm technology. I started off with a Dickson charge pump and also tried pelliconi charge pump. But in both cases the output current is in micro amperes range. I am using 1Mhz clock and 10pf Cfly. Can anyone please suggest me a better topology to maximize my output current and any design methods which I should follow.

    Thanks!

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  2. #2
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    Re: Charge pump topology

    Quote Originally Posted by bharath_k View Post
    charge pump
    ...
    0.8 V supply
    It's a challenge since you want to build an oscillating circuit which avoids the use of diodes because they subtract from output voltage.

    This simulation is a voltage doubler which works with transistors, and 0.8V supply. It illustrates what's possible if it could be adapted to your spec 22nm.

    Click image for larger version. 

Name:	astable H-bridge 6 transis 1V supply 2 cap V dblr 300 ohm load gets 1_8V.png 
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    The stacked capacitors receive alternating current at the center of an H-bridge (consisting of the two rightmost half-bridges). Each capacitor acquires supply voltage.

    Clock signals originate in the left H-bridge (consisting of the two leftmost half-bridges).
    Thus the middle half-bridge does double duty.

    - - - Updated - - -

    Conceivably you could install an identical voltage doubler where the load is, thus making a self-oscillating voltage quadrupler, from a 0.8V supply.



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  3. #3
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    Re: Charge pump topology

    Hi Brad,

    Thanks for your reply. May be I didn't explain my application clear. I don't want an oscillating circuit. I want a DC-DC converter. The application where this charge pump to be used is for Neurostimulation.

    Thanks.



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  4. #4
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    Re: Charge pump topology

    This voltage multiplier is a Nakagome type. Capacitors charge in parallel, discharge in series.

    Additional stages can be added until output is 3.3 V to your load. This schematic is a tripler, to demonstrate how stages are cascaded. The method is to attach half-bridges in combination. It may be possible to get correct bias for each transistor by tapping for voltage changes at strategic nodes.

    Click image for larger version. 

Name:	Nakagome tripler clk-driven 500kHz 2 caps 7 transis 0_8V supply.png 
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    Clock pulses are applied at left (which you shall provide since you claim you don't need an oscillator).


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  5. #5
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    Re: Charge pump topology

    Thanks a lot. I will work on this and let you know the result.



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