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  1. #1
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    ERROR:HDLParsers:709

    Dear all Gurus and just good guys!
    Pls tell me what's wrong with my code, top level file is in VHDL , lower level file is Verilog,why i get this kind of error ?
    I remember that VHDL and Verilog works well in my old projects and this is not reason.

    Code:
    ERROR:HDLParsers:709 - "C:/Users/user1/Desktop/fpga_p/MT9/camera_v0.vhd" Line 229. Reset_Delay is not an entity name
    
    signal DLY_RST_1, DLY_RST_0,DLY_RST_2:  std_logic;
    
    U1:  entity work.Reset_Delay 
     PORT MAP( iCLK       => clk96,
    		  iRST       => rst_n,
    		  oRST_0     => DLY_RST_0,
    		  oRST_1     => DLY_RST_1,	
    	          oRST_2     => DLY_RST_2 );
    
    module	Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2);
    input		iCLK;
    input		iRST;
    output reg	oRST_0;
    output reg	oRST_1;
    output reg	oRST_2;

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  2. #2
    Advanced Member level 5
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    Re: ERROR:HDLParsers:709

    Try to declare the component prototype of "Reset_Delay" in the .VHD file where you instantiate it - instead of instantiating it from work.reset_delay.


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  3. #3
    Advanced Member level 5
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    Re: ERROR:HDLParsers:709

    VHDL has no knowledge of Verilog. Hence directly accessing a Verilog module from a vhdl library is illegal because it doesnt exist.
    You need to use a component to give the VHDL compiler knowledge of what the entity is, then let the tool map that component to a Verilog module.


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