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    Using multilayer AHB-Lite

    I tried posting this thread earlier but it just vanished, so hope it doesnt appear twice.

    I am doing a masterthesis where the AHB protocol is a central subject, and I am confused about
    where we use multilayer AHB-Lite instead of AHB.

    I should not describe all the details as it is not relevant, but I am designing wrappers to our masters
    and slaves, and the goal is to automatically generate either an AHB-LIte or AHB system from
    an abstract model, where type depends on the model attributes.

    So far I have a working single layer AHB-Lite system, and the next step is to add more masters.

    Will it be beneficial to use multilayer AHB-Lite as an inbetween to the AHB-Lite and the AHB?
    Or does the multilayer only give advantages in terms of design flexibility and bandwidth?

    any thoughts here are very welcome

    best

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  2. #2
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    Re: Using multilayer AHB-Lite

    In my opinion a multi-layer AHB-Lite is not often employed.
    As I see it, for each layer of AHB-Lite there will be a master. And these masters should also remain connected.
    So why not directly have a AHB system, instead of AHB-Lite multi-layer, where multiple masters and multiple slaves comes into the picture.
    Moreover in my opinion it is probably easier to manage a multi-master/slave AHB system rather than a multi-layer AHB-Lite system.
    FPGA enthusiast!


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    Re: Using multilayer AHB-Lite

    I read somewhere someone advocating the use of multilayer as most slaves aren't split capable anyway, therefore saving area on arbitration
    logic and less complex masters. But if I understand correctly, each master has its own interconnect layer so the area argument doesn't seem right.

    What about managing a multilayer system is harder than a multi-master AHB system?
    The multi-master arbitration and master logic seem very complex.



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  4. #4
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    Re: Using multilayer AHB-Lite

    I read somewhere someone advocating the use of multilayer as most slaves aren't split capable anyway, therefore saving area on arbitration
    logic and less complex masters. But if I understand correctly, each master has its own interconnect layer so the area argument doesn't seem right.
    Correct.
    There are many types of arbitration schemes that can be employed and each one has its own complexity + merits/demerits.
    FPGA enthusiast!



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