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large slack (Reg2Reg) after placement (IC Compiler & Physical design)

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Dan_Yang

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Hi,

I used the ddc file from DCT, and executed floorplan and placement. Timing slack after DCT is tolerable(0.6), while after placement is 8.2.
Here are what i did.
1. created_fp_placement -effort high
2. place_opt -spg -optimize_dft -area_recovery -power
3. run" incremental opt"

And here are my questions:
(1) what else can I do to minize timing slack
(2) what the placement is based on? i mean how does icc know where to put a specific cell. Since I doubt whether I missed set timing constraints for it,( like sdc in DC&DCT).

Looking forward to your kind help!
 

More slack is a good thing, not a bad thing. Why do you want to reduce it?
 

Sorry, I intended say slack is -0.6, -8.2.
 

Dan_Yang said:
Sorry, I intended say slack is -0.6, -8.2.
Click to expand...

this is pretty normal, timing degrades as the analysis becomes more fine-grained. you have to now identify the source and move on. maybe you need more area, maybe better floorplan, maybe RTL changes, maybe tighter constraints... now is the time to use your engineering brain.
 

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