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  1. #1
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    How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retiming.

    Hi,

    I have a RTL to synthesize and PnR with power as highest priority. Timing should just met.
    I dont have libs to support UPF or multi vdd, clock gating. I tried retiming at synthesis, but retimable flops are clocked with different clocks.

    Tools: Genus, Innovus

    Power target after routing in PnR= 20uW
    Achieved power after synthesis= 370uW

    Could anyone suggest best remedy so that I can get close to 20uW after routing?

  2. #2
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    Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    Quote Originally Posted by asic_architect View Post
    Hi,

    I have a RTL to synthesize and PnR with power as highest priority. Timing should just met.
    I dont have libs to support UPF or multi vdd, clock gating. I tried retiming at synthesis, but retimable flops are clocked with different clocks.

    Tools: Genus, Innovus

    Power target after routing in PnR= 20uW
    Achieved power after synthesis= 370uW

    Could anyone suggest best remedy so that I can get close to 20uW after routing?
    none of this makes sense. let's start with the basics... why can't you use clock gating?
    Really, I am not Sam.



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  3. #3
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    Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    Genus says libs dont have clock gating cells.



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    Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    Quote Originally Posted by asic_architect View Post
    Genus says libs dont have clock gating cells.
    Are you forcing genus to use ICG cells? In theory, any AND gate is enough to create the clock gating behaviour.
    Really, I am not Sam.



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    Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    No. I am not forcing Genus to use ICG. Heres my run details

    1. A standard run script
    2. See how much power you are getting
    3. In the next run, to reduce the power I tried using "set_db lp_insert_clock_gating true" and got that message "libs dont have clock gating cells"

    Please let me know if this is the correct approach or what can be done to achieve the power target mentioned in the question. How much should I aim for synthesis stage and how much can I optimize in PnR.



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    Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    Quote Originally Posted by asic_architect View Post
    No. I am not forcing Genus to use ICG. Heres my run details

    1. A standard run script
    2. See how much power you are getting
    3. In the next run, to reduce the power I tried using "set_db lp_insert_clock_gating true" and got that message "libs dont have clock gating cells"

    Please let me know if this is the correct approach or what can be done to achieve the power target mentioned in the question. How much should I aim for synthesis stage and how much can I optimize in PnR.
    try playing with the root attribute lp_insert_discrete_clock_gating_logic
    Really, I am not Sam.



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    Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    Can you use high Vt Cells if timing allows? This will reduce static power though.



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    Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    Quote Originally Posted by swabhi812 View Post
    Can you use high Vt Cells if timing allows? This will reduce static power though.
    I think he is struggling with dynamic power. Either way, a mix of LVT/RVT/HVT cells will help bring dynamic and static power down. This alone won't get you a one order of magnitude reduction in power though.
    Really, I am not Sam.



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    Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    Thanks for your response.
    I am already using HVTs though.



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    Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    Yes. I am struggling with Dynamic power (Internal power is 77% of total power).

    Power target after routing: 20uW
    Achieved power after synthesis: 370uW

    Can I bring it down that much during PnR somehow or should I change the libraries and synthesize again?
    How much power should I am at synthesis stage if 20uW is a target after routing?



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  11. #11
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    Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    Quote Originally Posted by asic_architect View Post
    Yes. I am struggling with Dynamic power (Internal power is 77% of total power).

    Power target after routing: 20uW
    Achieved power after synthesis: 370uW

    Can I bring it down that much during PnR somehow or should I change the libraries and synthesize again?
    How much power should I am at synthesis stage if 20uW is a target after routing?
    Most likely no, you won't come even close to 20uW. But there is so much I don't follow in this discussion... you should be able to use retiming without special flops and you should be able to use clock gating without ICG cells. There is also the issue of power estimation on itself, it is only as accurate as the input vector you provide to it.
    Really, I am not Sam.



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