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  1. #1
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    VHDL: reading text file stops at endfile()

    Hello Everyone,

    I am implementing a test bench which will load the input stimuli vectors from a text file and save the resulting vector in another text file. While it was rather simple to write in a file, it is not so obvious for me how to read the file.

    Below is a shorted part of test bench only to check if it can read the file:

    Code:
    library IEEE;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use std.textio.all;
    use ieee.std_logic_textio.all;
    
    entity CARRY_LOOKAHEAD_ADDER_TB is
        generic(
                VECTOR_LENGTH : natural := 98;
                MEMORY_DEPTH  : natural := 32;
                ADDRESS_WIDTH : natural := 6
                );
    end entity CARRY_LOOKAHEAD_ADDER_TB;
    
    architecture BEHAVIOURAL of CARRY_LOOKAHEAD_ADDER_TB is
        
        type MEMORY is array (0 to MEMORY_DEPTH - 1) of std_logic_vector(VECTOR_LENGTH - 1 downto 0);
        
        signal CLK : std_logic;
           
        signal TEST_DATA_MEMORY  : MEMORY;
    
        signal ADDRESS : natural range 0 to (2**ADDRESS_WIDTH - 1);
        signal ADDRESS_NEXT : natural range 0 to (2**ADDRESS_WIDTH - 1);
        signal NUMBER_OF_ERRORS : natural range MEMORY_DEPTH - 1 downto 0;
        
        file   TEST_DATA: text;
                   
    begin
        
        process
        begin
            CLK <= '1';
            wait for 5 ns;
            CLK <= '0';
            wait for 5 ns;
        end process;
        
        
        CI <= '0';
        
        file_open(TEST_DATA,   "cla_tb_v.txt", read_mode);
                
        process
            variable TEST_VECTOR : line;
            variable MEMORY_WORD : std_logic_vector(VECTOR_LENGTH - 1 downto 0);
        begin
            
            while not endfile(TEST_DATA)loop
                readline(TEST_DATA, TEST_VECTOR);
                read(TEST_VECTOR, MEMORY_WORD);
                TEST_DATA_MEMORY(ADDRESS) <= MEMORY_WORD;
            end loop;
         
            wait;
    end process;
    
    end BEHAVIOURAL;
    Simulation stops at the line:
    Code:
    while not endfile(TEST_DATA)loop
    And thus no data are read from the file.

    I checked the status upon the file opening and the status is OPEN_OK. The text file to read is not empty, please see below for a snapshot of the file:
    Code:
    00000000000000000000000000000001011111111111111111111111111110000111111111111111111111111111100100
    00000000000000000000000000000001011111111111111111111111111110010111111111111111111111111111101000
    00000000000000000000000000000001011111111111111111111111111110100111111111111111111111111111101100
    00000000000000000000000000000001011111111111111111111111111110110111111111111111111111111111110000
    I definitely do a mistake, but I do not see it. Please advise.

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  2. #2
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    Re: VHDL: reading text file stops at endfile()

    You have the file open procedure outside of a process. It is hitting the while loop before the file is open.

    Either open the file at the declaration or move the open procedure inside the process before the while loop.


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  3. #3
    Super Moderator
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    Re: VHDL: reading text file stops at endfile()

    Wrongly placed file_open() statement. Has to go in the process before the loop.


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  4. #4
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    Re: VHDL: reading text file stops at endfile()

    Thank you! That closes the question.



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