wes_s01
Newbie
Hello, newer designer here so please bear with me.
I am designing a clock distribution circuit where minimizing additive jitter is critical. I am driving 2 equal length wirelines with two large inverters, taking care to use the smallest resistance metal layer available to me.
This is the measured phase noise at the output of the load.
I'm using ADE L and spectre for simulations, and am seeing these large spurs around the harmonics. Given the phase noise is approximately -51 dBc at 100M, I refered to Silicon Labs application note AN256 and determined the jitter due to that spur is about 6.34 ps, which I need to reduce.
I'm curious if someone could explain what might be the cause of these spurs in the buffer/wireline circuit and how I might reduce these deterministic noise components.
Thank you,
I am designing a clock distribution circuit where minimizing additive jitter is critical. I am driving 2 equal length wirelines with two large inverters, taking care to use the smallest resistance metal layer available to me.
This is the measured phase noise at the output of the load.
I'm using ADE L and spectre for simulations, and am seeing these large spurs around the harmonics. Given the phase noise is approximately -51 dBc at 100M, I refered to Silicon Labs application note AN256 and determined the jitter due to that spur is about 6.34 ps, which I need to reduce.
I'm curious if someone could explain what might be the cause of these spurs in the buffer/wireline circuit and how I might reduce these deterministic noise components.
Thank you,
