Shifting control from one module to another iteratively

I have two separate modules that iterate over a range. One generator module will produce input for DUT and this data goes to another module that works on this data iteratively. I tried to code this but somehow I do not know how to transfer the control from one block to another step by step. Can anyone help?

Hi,

Could you be more specific?
You just give very vague inoirmations.

Klaus

KlausST said:

Hi,

Could you be more specific?
You just give very vague inoirmations.

Klaus

Click to expand...

Hi,

I wish to have an input generator module that will generate data iteratively. Every time it generates a data, I want another module to perform a function on this data and send it to the DUT. Then again , I want my generator to send out a different data to the second module which will carry out the same process again.

Your description brings to mind a chess clock. It contains two stopwatches. One player's watch runs while he considers what move to make. When he decides, he makes his move, then hits a push-switch which stops his watch and at the same time tells the other player's watch to start.

What action takes place, that decides it's time for your two modules to switch tasks?

Electronically the action is a SR flip-flop. When the action occurs, have that module send a pulse to its side of the flip-flop. The flip-flop changes state and remains that way, until the other module sends a pulse to its side of the flip-flop.

Or, in software create a global variable X which can have either the value 1 (for module #1), or 2 (for module #2). As your program executes, designate the sending module as X. Designate the receiving module as 3-X. Whenever X changes, the value of 3-X automatically (everywhere it occurs in the program) designates the other module. It works in IF-THEN statements and in arrays.

Step 1, create a vector-array of your data
Step 2, Use generate statements to iteratively connect the previous.



It's worth stating that array_range may be smaller than ACTUAL array_range to account for the +1 offset etc.

I hope this is an avenue worth exploring.

Regards,


-----------------
Edit#
I read other replys and see my response is not relevant to question, but useful nonetheless for #1

wesleytaylor said:

Step 1, create a vector-array of your data
Step 2, Use generate statements to iteratively connect the previous.

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
type x is array<> of std_logic_vector(<>)
signal data_in : x ... -- note this is pseudo code.
...
 
G_label : for I in array_range generate --loop
begin
    uut : component
        port map
        (
            clk => clk,
            ...
            data_in => data_in(I),
            data_out => data_in(I+1),
        );
end generate;

---

It's worth stating that array_range may be smaller than ACTUAL array_range to account for the +1 offset etc.

I hope this is an avenue worth exploring.

Regards,


-----------------
Edit#
I read other replys and see my response is not relevant to question, but useful nonetheless for #1

Click to expand...

OP has been asking questions in Systemverilog not VHDL, this sample of code isn't going to help them.

Another way besides the SR control is use SV queues, just fill two queues in the module that interleaves, which is what it appears you are trying to convey with "that works on this data iteratively") the two input separate modules data. This way you can interleave the two inputs any way you want and start or stop the module that feeds the interleaved data to the DUT and you won't have to rely on a global control variable.

ads-ee said:

OP has been asking questions in Systemverilog not VHDL, this sample of code isn't going to help them.

Another way besides the SR control is use SV queues, just fill two queues in the module that interleaves, which is what it appears you are trying to convey with "that works on this data iteratively") the two input separate modules data. This way you can interleave the two inputs any way you want and start or stop the module that feeds the interleaved data to the DUT and you won't have to rely on a global control variable.

Click to expand...

Hi,

Thank you for your reply. I had a query about incorporating a clock in the two modules. What if the two separate modules are run on a clock? Will that mean in one posedge of clock, the first data gets fed in; goes to the next module which will iterate over a few iterations and control goes back to generator module?

rrucha said:

Hi,

Thank you for your reply. I had a query about incorporating a clock in the two modules. What if the two separate modules are run on a clock? Will that mean in one posedge of clock, the first data gets fed in; goes to the next module which will iterate over a few iterations and control goes back to generator module?

Click to expand...

Given the vague specification of your requirements. I would once again suggest using SV queues, then it won't matter if you use clocks or not, the two modules will send their data to the third module and the third module will just read from the queues and output data to the DUT in whatever fashion or interleave pattern you want.

I think you need to draw up a high level block diagram of your testbench to get a better idea of how everything is interconnected and controlled.

I think this thread is somehow related to this post:
https://www.edaboard.com/showthread.php?386251-SystemVerilog-Input-generation

Dear OP, I am not sure regarding your understanding of modules, blocks, etc.....

I have two separate modules that iterate over a range. One generator module will produce input for DUT and this data goes to another module that works on this data iteratively. I tried to code this but somehow I do not know how to transfer the control from one block to another step by step. Can anyone help?

Click to expand...

As I and others have told you in other posts, to ease understanding, please post the RTL for quality help.