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    SystemVerilog Input generation

    I want to test my code which has a 256 bit input. I want my testbench to have a generator to generate a ramp input in order to test all possible input combinations but in a ramp fashion. What I mean by this is, if we have a 4 bit input data that needs to be used, in order to test all of the cases we should be able to provide the DUT with inputs likes 0000, 0001, 0010, 0100 ....... 1111
    So basically for a 256 bit input I should cover all 2^256 cases. This needs to be done in an ordered manner. I want to automate this in my testbench. Does anybody know how to do this?

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    Re: SystemVerilog Input generation

    Hi,

    No chance to test all 2^256 combinations.
    Forget this idea.

    Even with an 1GHz test frequency it takes about 10^59 years .... if my mind calculation is correct.

    Klausg

    Even if it's not correct ... it will be close to eternity....
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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    Re: SystemVerilog Input generation

    This is a pretty worthless activity. Why do you need to? Is this a data bus carrying packets? You need to look into constrained random testing.



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    Re: SystemVerilog Input generation

    I do not need to test all the combinations. Say even 2^16 of the first combinations out of the 2^256. But in an increasing manner. How could I achieve that? Its basically to cover all cases while testing.

    - - - Updated - - -

    Could someone please help me? This is constrained input generation.



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    Re: SystemVerilog Input generation

    You should keep in mind what others have suggested.

    Could someone please help me? This is constrained input generation.
    You can have something like...
    process for 256 bits up-counter in TB --> DUT --> process for checking the DUT output/s

    What is your exact difficulty in writing a test-bench?
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    Re: SystemVerilog Input generation

    Quote Originally Posted by dpaul View Post
    You should keep in mind what others have suggested.


    You can have something like...
    process for 256 bits up-counter in TB --> DUT --> process for checking the DUT output/s

    What is your exact difficulty in writing a test-bench?
    Thank you for your reply. The difficulty is that my testbench is performing another operation ; something of error injection. This module repeats for a few cyles. I want the generator to be a separate module and for every input that is generated for the DUT, I want my error module to alter the data and send it to the DUT.



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    Re: SystemVerilog Input generation

    I want the generator to be a separate module and for every input that is generated for the DUT, I want my error module to alter the data and send it to the DUT.
    That should also not be difficult.
    For such operations just keep 2 separate always blocks in the testbench, one for incrementing counter data and other for generating error data. Once your counter in process1 has incremented, you can use this value in process2 to generate the error data and feed it to the DUT.
    Last edited by dpaul; 29th August 2019 at 08:29.
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    Re: SystemVerilog Input generation

    Quote Originally Posted by dpaul View Post
    That should also not be difficult.
    For such operations just keep 2 separate always blocks in the testbench, one for incrementing counter data and other for generating error data. Once your counter in process1 has incremented, you can use this value in process2 to generate the error data and feed it to the DUT.
    Thank you for your reply. So I am guessing I will have to add a clock to govern the two processes? Both the modules will execute, say on the positive edge of the clock. Is that correct?

    - - - Updated - - -

    It doesnt seem to work. I made the input generator as a counter module. It keeps counting and sends some random data in between to the error module. I do not understand how I can synchronize them in such a way that one single data gets sent every iteration.



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    Re: SystemVerilog Input generation

    Quote Originally Posted by rrucha View Post
    It doesnt seem to work. I made the input generator as a counter module. It keeps counting and sends some random data in between to the error module. I do not understand how I can synchronize them in such a way that one single data gets sent every iteration.
    Without code or even a diagram of the structure of your testbench it is nearly impossible to tell you what is wrong.

    Based on the limited information in this post. If a counter has a clock it will keep counting, it doesn't generate random data on it's own.

    Between the two threads you have I don't think you are approaching this correctly.



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    Re: SystemVerilog Input generation

    Hi,

    I will make it simple. I have one error module that is injecting error. I have a for loop in that which allows it to inject errors at random locations over and over again. This works perfectly when I give it just one data input from the testbench (as a part of the initial block). Now when I make a small change of adding a second input data, my error module only takes the last data and works on it. My error modules works in the always@(data) block so it should work on the data everytime a new data comes in.



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    Re: SystemVerilog Input generation

    Quote Originally Posted by rrucha View Post
    Hi,

    I will make it simple. I have one error module that is injecting error. I have a for loop in that which allows it to inject errors at random locations over and over again. This works perfectly when I give it just one data input from the testbench (as a part of the initial block). Now when I make a small change of adding a second input data, my error module only takes the last data and works on it. My error modules works in the always@(data) block so it should work on the data everytime a new data comes in.
    This doesn't make it simple. Word descriptions are not the simplest way to get a fix for something like this, which might be an issue with your understanding of Systemverilog or of how the simulator works or something else entirely.
    e.g.
    Now when I make a small change of adding a second input data, my error module only takes the last data and works on it.
    What does this even mean? If the error module only takes the last data and works on it how do you know that it worked on the last data twice? Did you add anything to debug your loop? Maybe you have an infinite loop I don't see any code so can only make guesses.

    If you can't post your real code then write a sanitized testcase that exhibits the same problem you are experiencing and post that so someone can actually help you out.



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    Re: SystemVerilog Input generation

    Sure.
    I have modules : encoder, decoder, error (this flips random bits of data and sends it to the encoder which then sends it to the decoder which corrects the data).
    I havent used any clock. I have a testbench which sends the data to the error module as well as parity module (as this parity is used along with my input data; and this entire data is used to flip a single bit in error module).
    i have a for loop in error module which lets me add errors at different locations and check if my decoder does its job.
    Now, when I send a second data (with a delay), all these module use the last data to do their job. And the first data only displays ( i have display statements in my testbench)



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    Re: SystemVerilog Input generation

    Quote Originally Posted by rrucha View Post
    Sure.
    I have modules : encoder, decoder, error (this flips random bits of data and sends it to the encoder which then sends it to the decoder which corrects the data).
    I havent used any clock. I have a testbench which sends the data to the error module as well as parity module (as this parity is used along with my input data; and this entire data is used to flip a single bit in error module).
    i have a for loop in error module which lets me add errors at different locations and check if my decoder does its job.
    Now, when I send a second data (with a delay), all these module use the last data to do their job. And the first data only displays ( i have display statements in my testbench)
    All you keep doing is telling us in text what you are doing. What you are doing is obviously wrong. It is the implementation details of your described testbench code that is at fault. Without the code or a testcase of the code nobody is going to be able to tell you why your testbench doesn't work.

    Unless you post some code (either the actual code or a sanitized test case) I give up helping you on both of your threads.



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    Re: SystemVerilog Input generation

    Dear OP, stop all those verbose and post your TB RTL if your really want to be helped.
    Last edited by dpaul; 30th August 2019 at 09:09.
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