Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

For doing ECO on netlist

Status
Not open for further replies.

fragnen

Full Member level 3
Joined
Apr 3, 2019
Messages
182
Helped
0
Reputation
0
Reaction score
1
Trophy points
18
Activity points
1,299
How can ECO be done on netlists without using Cadence ECO tool or any tool that needs to purchase a license? Is there any free tool? Is there any way to do it without tool?

Regards
 

Open the netlist using a text editor and hand-edit it (you should know what you are doing)! :p
 

Open the netlist using a text editor and hand-edit it (you should know what you are doing)! :p

It will be difficult when the number of gate counts is high for the ECO.
 

I know it is very difficult and is not standard practice. But you have a difficult limitation.
Maybe you should wait for other members to comment.
 

How can ECO be done on netlists without using Cadence ECO tool or any tool that needs to purchase a license? Is there any free tool? Is there any way to do it without tool?

Regards

How did you manage to do the physical design without a license?

This is nearly impossible to do with a free tool. Maybe there is a tool out there that can resize one gate for you in semi-automated fashion, but good luck finding something that will handle ecoPlace, ecoRoute, repeaters, shadow registers, and so on...
 

@not(Sam),

In 2012 a lead engineer from an ASIC design & verification service providing company told me proudly that they have hand-edited the dft inserted netlist (because bug/s were found by the verification guys) for some changes to be done as the Physical design team was unwilling to accept a new netlist. I don't know what's the motivation here.
 

@not(Sam),

In 2012 a lead engineer from an ASIC design & verification service providing company told me proudly that they have hand-edited the dft inserted netlist (because bug/s were found by the verification guys) for some changes to be done as the Physical design team was unwilling to accept a new netlist. I don't know what's the motivation here.

Interesting. I have seen people fudge with the netlist to fix simple mistakes (pin polarity at top level, for instance). But true hard ECO problems... there is no way. Say you try to upsize some cell by hand, believing it would improve performance. Then you run STA and realise that the new load makes the overall path slower. Without an automated tool, this is really hard to notice/accomplish.
 

Well I definitely believe you.
What change was actually done and how it was done was not discussed. It was just a casual chat, among many other talks, with someone you meet casually in the coffee room. Anyways, it was surprising for me then and now.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top