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    For doing ECO on netlist

    How can ECO be done on netlists without using Cadence ECO tool or any tool that needs to purchase a license? Is there any free tool? Is there any way to do it without tool?

    Regards

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  2. #2
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    Re: For doing ECO on netlist

    Open the netlist using a text editor and hand-edit it (you should know what you are doing)! :-p
    FPGA enthusiast!



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    Re: For doing ECO on netlist

    Quote Originally Posted by dpaul View Post
    Open the netlist using a text editor and hand-edit it (you should know what you are doing)! :-p
    It will be difficult when the number of gate counts is high for the ECO.



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  4. #4
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    Re: For doing ECO on netlist

    I know it is very difficult and is not standard practice. But you have a difficult limitation.
    Maybe you should wait for other members to comment.
    FPGA enthusiast!



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    Re: For doing ECO on netlist

    Quote Originally Posted by fragnen View Post
    How can ECO be done on netlists without using Cadence ECO tool or any tool that needs to purchase a license? Is there any free tool? Is there any way to do it without tool?

    Regards
    How did you manage to do the physical design without a license?

    This is nearly impossible to do with a free tool. Maybe there is a tool out there that can resize one gate for you in semi-automated fashion, but good luck finding something that will handle ecoPlace, ecoRoute, repeaters, shadow registers, and so on...
    Really, I am not Sam.



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  6. #6
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    Re: For doing ECO on netlist

    @not(Sam),

    In 2012 a lead engineer from an ASIC design & verification service providing company told me proudly that they have hand-edited the dft inserted netlist (because bug/s were found by the verification guys) for some changes to be done as the Physical design team was unwilling to accept a new netlist. I don't know what's the motivation here.
    FPGA enthusiast!



  7. #7
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    Re: For doing ECO on netlist

    Quote Originally Posted by dpaul View Post
    @not(Sam),

    In 2012 a lead engineer from an ASIC design & verification service providing company told me proudly that they have hand-edited the dft inserted netlist (because bug/s were found by the verification guys) for some changes to be done as the Physical design team was unwilling to accept a new netlist. I don't know what's the motivation here.
    Interesting. I have seen people fudge with the netlist to fix simple mistakes (pin polarity at top level, for instance). But true hard ECO problems... there is no way. Say you try to upsize some cell by hand, believing it would improve performance. Then you run STA and realise that the new load makes the overall path slower. Without an automated tool, this is really hard to notice/accomplish.
    Really, I am not Sam.



  8. #8
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    Re: For doing ECO on netlist

    Well I definitely believe you.
    What change was actually done and how it was done was not discussed. It was just a casual chat, among many other talks, with someone you meet casually in the coffee room. Anyways, it was surprising for me then and now.
    FPGA enthusiast!



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