D
daskk62
Guest
Actually I am working in an DSP alorithm, in the top module of my verilog code I called my data as given in attatched file. But when I am dumping bitstream in the FPGA Basys 3 kit ( LEDs as output) the FPGA is not showing any output. Why? can anybody help me to solve it. (It is working properly in the simulation phase but not in hardware). Also when I did the synthesis and run the post synthesis simulation in my Vivado 2018.2, it is only showing 0's in the output. please help me to solve it.
I am getting a warning when I ran the simulation
[Synth 8-6040] Register i_reg_rep driving address of a ROM cannot be packed in BRAM/URAM because of presence of initial value.
I am getting a warning when I ran the simulation
[Synth 8-6040] Register i_reg_rep driving address of a ROM cannot be packed in BRAM/URAM because of presence of initial value.