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  1. #1
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    My FPGA Basys 3 Board is not showing output?

    Actually I am working in an DSP alorithm, in the top module of my verilog code I called my data as given in attatched file. But when I am dumping bitstream in the FPGA Basys 3 kit ( LEDs as output) the FPGA is not showing any output. Why? can anybody help me to solve it. (It is working properly in the simulation phase but not in hardware). Also when I did the synthesis and run the post synthesis simulation in my Vivado 2018.2, it is only showing 0's in the output. please help me to solve it.

    I am getting a warning when I ran the simulation
    [Synth 8-6040] Register i_reg_rep driving address of a ROM cannot be packed in BRAM/URAM because of presence of initial value.

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    Re: My FPGA Basys 3 Board is not showing output?

    There is two different type of Verilog statements "Synthesizable" and "Non-Synthesizable".
    Some of the Verilog expression are simulation only. Therefore your rom data wont be loaded into register.
    http://www.asic-world.com/verilog/synthesis2.html



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  3. #3
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    Re: My FPGA Basys 3 Board is not showing output?

    Quote Originally Posted by Amadeus View Post
    There is two different type of Verilog statements "Synthesizable" and "Non-Synthesizable".
    Some of the Verilog expression are simulation only. Therefore your rom data wont be loaded into register.
    http://www.asic-world.com/verilog/synthesis2.html
    Don't think this has anything to do with the problem the OP is having. $readmemh is synthesiable, but I have never seen anyone put it inside a always block. It is typically done in an initial block (note this does work for FPGAs).

    You are also using blocking assignments in your edge sensitive always block, which can cause problems, you should always use non-blocking assignments in edge sensitive always blocks.

    Don't know if either of those is the issue, but with the posted code that doesn't show how imff1 is generated, those are the two issues I see in the code. Removed both instantiations and the rom_memory loads in simulation, but as it is not in an initial block so it is being loaded every clock cycle which is not possible, so perhaps this might be ignored by synthesis (simulation doesn't care).

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    Quote Originally Posted by daskk62 View Post
    I am getting a warning when I ran the simulation
    [Synth 8-6040] Register i_reg_rep driving address of a ROM cannot be packed in BRAM/URAM because of presence of initial value.
    Also this is not a simulation warning it is a synthesis warning. Besides this you should be using a standard template to infer a RAM/ROM in your code. This usually means NO reset on the RAM/ROM always block. If you have resets it ends up having problems packing registers into the RAM blocks as the synthesis message indicates.



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