Boost PFC controller must contain anti-distortion feature for zero crossings

Pages 22 and 23 of the L6564 datasheet show that Boost PFC controllers need to sense the instantaneous mains voltage, and then increase the FET current at the zero crossings. This is to reduce crossover distortion and thus reduce THD.
Why does the LT1248 PFC controller not mention this feature? Does it not have this feature? How does it avoid the LC filter ringing that otherwise occurs near the zero crossing if this feature is not present?

L6564 datasheet
https://www.st.com/resource/en/datasheet/l6564.pdf
LT1248 datasheet
https://www.analog.com/media/en/technical-documentation/data-sheets/1248fd.pdf

LT1248 is from about 1999
see what looks like a date code at the bottom of the last page
1248fd LT/GP 0799 2K REV D • PRINTED IN USA
i think 0799 is a date, july 1999
package is a 16 pin plastic DIP - an "old" package
see page 6, the section on Pin 6, IAC, at the bottom

L6564 is from about 2013
note copyright on the last page
and date at the bottom of page 1
package is a SSOP10 - a "new" package

I think the difference is that the ST part is newer and has the feature added
to help correct an issue with the older version

The assumption implied by the title is wrong. A boost PFC must not necessarily contain this feature to comply with power quality regulations.

average current mode PFC chips ( like the original UC3854 ) automatically raise the PWM around the zero xing to keep the average input current tracking the mains voltage waveshape - controllers like the 6564 are not average mode and so need extra bits to force them to go to higher PWM around the zero xing to help improve the power factor ...

average current mode PFC chips ( like the original UC3854 ) automatically raise the PWM around the zero xing to keep the average input current tracking the mains voltage waveshape

Click to expand...

Thanks… the attached (including LTspice sim) is a basic PWM controller that I’ve hacked to give average current mode power factor correction for a boost converter. I haven’t implemented the feature whereby the current is increased at the zero crossings. As you can see, there are unwanted blips in the mains input current waveform….these cannot be gotten rid of by adjusting the filter values etc…..i assume that the only way to get rid of this will be to somehow make the FET ON time higher at the zero crossings, which should damp out the sudden blip that occurs just after the zero crossing, where the mains bridge suddenly begins flowing current into the post bridge capacitance, which unfortunately stays a little charged up and so causes this blip.
So what do you reckon?…I should put in a zero crossing detector and just artificially increase the reference voltage near the zero crossings so as to discharge the post bridge capacitance at the zero crossing?...that will get rid of the blipping?

Or should i just forget it...it surely wont give a failure of THD?

most design engineers would not worry about such a small artifact, it does indeed loo to be caused by bridge rect noise - and would be filtered by the EMC filters ...

most design engineers would not worry about such a small artifact, it does indeed loo to be caused by bridge rect noise - and would be filtered by the EMC filters ...

Click to expand...

Thanks but that is in the mains input current , albeit the simulator....but it didnt get filtered out, and i find even increasding the fitration doesnt solve it......but as you say, it looks like it can be ignored.

it looks to be more an artifact of the diode bridge in the sim - this is quite common to see - try putting a snubber across each diode in the sim to remove ...

Thanks, back on this subject, i wonder why the L4981 is so much cheaper than the LT1248? They are both average mode PFC controllers...

The L4981 and LT1248 are both essentially exactly the same apart from one significant difference….The LT1248 has a “line current dead zone reduction” feature. (By way of the Bias current from the CAOUT pin, and the low bias voltage of the IAC pin). This is a great feature for PFCs because it means that you get far less LC input filter ringing at the mains zero cross….and hence far less THD.
This is because it draws an additional current at the zero crossings.

I actually went to a company once where they had layed out a 600W PSU with a ti.com PFC chip which didn’t have this feature, and it had dreadful line current distortion at the zero crossings……the whole thing had to be scrapped and re-done.

Do you believe that this is why the LT1248 is so much more expensive than the L4981? (its at least double the price)

LT1248
https://www.analog.com/media/en/technical-documentation/data-sheets/1248fd.pdf
L4981
https://www.st.com/content/ccc/reso...df/jcr:content/translations/en.CD00000085.pdf

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On a similar note, the IR1155 PFC controller is cheaper than either LT1248 or L4981.

However, the IR1155 has no way of handling zero cross distortion (they just tell you to minimise the post bridge capacitor). Also, despite being an average current mode controller, the IR1155 can only be used in deep CCM. This is a bad thing, since LT1248 & L4981 can do it in DCM…which means less reverse recovery stress on the boost diode. Indeed LT1248 and L4981 can operate with CCM and DCM modes occurring in the mains half cycle. Would you agree with all this?

IR1155
https://www.infineon.com/dgdl/an-1166.pdf?fileId=5546d462533600a40153559aabdf1128

LT1248
https://www.analog.com/media/en/technical-documentation/data-sheets/1248fd.pdf

L4981
https://www.st.com/content/ccc/reso...df/jcr:content/translations/en.CD00000085.pdf