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    Lattice FPGAs and Diamond software

    Hi Folks;

    I've been looking for a low cost, high speed(500MHz data aqu) FPGAs. I'm familiar with altera and quartus but I'm wondering about Lattice.
    I would be grateful if you could share your expericence with Lattice.

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    Re: Lattice FPGAs and Diamond software

    THe ECP5 family can be clocked above 200 MHz for the logic.
    For the I/O you can have at least 400 MHz DDR = 800 Mbit/s per pin.

    The Diamond software is not as good as what Xilinx and Altera have.
    For ECP5 devices without SERDES, the Diamond license is free.


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    Re: Lattice FPGAs and Diamond software

    I've used Lattice (on and off for 15 years or so), Xilinx (A lot in the last 10 years or so) and Altera (one project recently).

    In terms of tool quality the ranking is pretty clear:
    1) Xilinx Vivado
    2) Altera Quartus + Modelsim
    3) Lattice Diamond + Aldec

    Lattice improves if you use Modelsim but I find it a huge penalty to use two tools for synthesis and simulation. Quartus shocked me with their poor modelsim integration requiring me to mess with script files and libraries. Vivado, while still having a few things that will drive you crazy until you give up caring, is clearly the most advanced IDE including robust syntax highlighting among other modern features.

    In terms of parts I'd say Lattice Machxo parts are quite competitive on the low end (and basically owned that market until the MAX10 came out). I've never seriously shopped Lattice for mid or higher end parts. In the mid to higher end my very general impression is that Xilinx and Altera are head-to-head though I think Xilinx Zynq is ahead of Altera's CPU+FPGA solutions.


    For 500Mhz data processing you need to be careful. MachXO or Max10 may be able to move the raw bits through a DDR interface but you need to make sure your processing from then on is realistic. I think the answer is to download the tools for the parts you're seriously considering and simulate what you want to do. You'll get tool familiarity and verification of your part choose at the same time.


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    Re: Lattice FPGAs and Diamond software

    Since Intel bought altera, they are heading for the server market and focusing only on high-end, moving towards having CPU and FPGA on the same die so they can get high throughput between CPU and FPGA - with huge support for OpenCL.
    Xilinx captured the Embedded CPU Market with their Zynq, Altera had a very weak and late attempt with the cyclone Soc and then basically binned it.
    If you are a VHDL user - the Vivado is only just (2019.1) adding half decent VHDL 2008 support. Quartus has had it for several years.
    Vivado Simulator is fine for basic stuff, but a waste of time for proper verification. Modelsim or Aldec are your only real options for this. Still no VHDL 2008 support for simulation (the synth now has better support than Simulation - odd)
    Im now a heavy Vivado user, and honestly its hugely over-bloated. Quartus was a very usable compiler with Timequest being a good tool, and it had full SDC support (and has done for nearly 10 years). Quartus feels light weight compared to Vivado. Vivado also has this annoying habit of trying to take over control of your files. Quartus just does what it's told.

    Xilinx have historically had a poor synthsis engine, and you could get better results with 3rd party synthesis (eg. from synopsys). Synopsys would openly admit that they could do no better than Quartus.

    As for Aldec Vs Modelsim. Modelsim is usually the go-to tool. But ActiveHDL is MUCH cheaper. They also respond very fast to bug reports and will usually give you patches. Never got anything like that from Mentor.

    Altera's IPs have always been much more user friendly. For example, the Altsyncram was a user configurable ram that the user could just instantiate and customise in their code. Xilinx forced you to generate a core for each and every ram you wanted, causes project bloat and it a pain to maintain or migrate. The XPM library has only just appeared for Ultrescale devices that gives the same functionality as the Altera Megafunctions, 10-15 years later than Altera.

    IMO, Altera Docs have always been better than Xilinx. Altera will give detailed interface info, with very useful timing diagrams etc. Xilinx in comparison feels very basic.


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    Re: Lattice FPGAs and Diamond software

    Quote Originally Posted by TrickyDicky View Post
    Xilinx have historically had a poor synthsis engine, and you could get better results with 3rd party synthesis (eg. from synopsys). Synopsys would openly admit that they could do no better than Quartus.
    At some point while still on ISE they dumped their own internal synthesis engine and bought a third party engine that was much better. It was around that time frame I was in a training class and there was ISE, Synplify, and Leonardo on the machines. I ran all the designs they had through all three tools. The performance of ISE's new synthesis engine was comparable to Synplify. In most cases (maybe 60%) it resulted in designs that had better maximum clock frequency. Leonardo on the other hand was pretty much always the worst.

    Quote Originally Posted by TrickyDicky View Post
    IMO, Altera Docs have always been better than Xilinx. Altera will give detailed interface info, with very useful timing diagrams etc. Xilinx in comparison feels very basic.
    I somewhat disagree. Xilinx used to have far better documentation than Altera (10+ years ago). Xilinx documentation was straight to the point and gave you information on the part. The problem I had with Altera back then was documents filled with "market speak". Paragraphs filled with comments about how great their parts were compared to the competition and how they were best in class. Even in the most technical sections of the documentation you would find embedded sections of market speak. Way too much sifting had to be done to find the gems.

    They eventually changed this starting around Cyclone 3 parts, after I complained rather loudly and on multiple occasions about this issue to the FAE and some of the marketing higher ups that visited the company I was working for at the time. I even pointed out sections of the documentation that had the problem after they asked me for examples (they weren't hard to find since there were so many of them). So perhaps my critical complaints help improve the documentation.


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    Re: Lattice FPGAs and Diamond software

    My main point of comparison was an RapioIO core I had to interface to in both an Altera and Xilinx device with the same code.
    Altera showed nice clean diagrams with all of the packet headers listed in the data bus so it was easy to work out how to frame a packet. In Xilinx, there was none of this - just a list of D0, D1... etc. It also didnt document the fact that one header was passed in via the tuser signal and the rest of the packet was shifted 1 byte because of it (they inserted it an re-aligned it internally. I had to had a back and forth with a Xilinx technical guys, who took a couple of weeks to get a reply from, to get a clear example of how the design worked. Having read other similar docs, I still think this comparison holds.
    Another annoyance is how Xilinx and Altera frame their Dwords. Xilinx make everything little endian, which means often get situations where you have a 16 bit word with MSBs and LSB switched around, meaning you need to flip the whole bus to make debugging possible. Altera just makes everything big endian from the start for easier debugging in a waveform.

    Ive only been doing this for 15 years, and so maybe I missed the earlier docs you describe.


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