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  1. #1
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    LDO Simulation Output Results

    I attempted to design a PMOS Pass Transistor LDO and obtained the following result.

    I set the reference voltage to about 650mv and did a DC simulation.

    The regulated voltage starts up and then dies as the VDD is ramped up.

    What could be causing this ?

    Thank you.

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  2. #2
    Advanced Member level 5
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    Re: LDO Simulation Output Results

    Positive feedback when you wanted negative?

    Looks like you are only passing the dV/dt from supply
    to output and only when FETs are weak. Maybe you
    have something disconnected.

    You know what really helps circuit discussions? Right.



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