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  1. #1
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    Comparator gives wrong Output

    Hi guys,

    I had been practicing a few problems in verilog and got stuck on this :

    Question : write a program so that output should be 1 when 'x' is greater than or equal to 'y'
    x and y are binary

    My logic module:

    Code Verilog - [expand]
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    module comparator(
    input x,
    input y,
    output z);
     
    assign z = ~y + x ;
    endmodule

    My stimulus/ test-bench module :

    Code Verilog - [expand]
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    `timescale 1ns / 1ps
    module stimulus;
    reg x;
    reg y;
    wire z;
    comparator uut (
        .x(x),
        .y(y),
        .z(z)
        );
    initial
    begin
    x=0;
    y=0;
    #20 x=1;
    #20 y=1;
     
    #20 x=0;
    #40;
     
    end
    initial
    begin
     
    $monitor("x=%d, y=%d, z=%d \n",x,y,z);
     
    end
    endmodule
    --------------------------------------------

    OUTPUT OBTAINED:

    Click image for larger version. 

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    Please Help with the above issue, output is shown as 0 when x=1 and y=0.

    Thank you!!
    Last edited by ads-ee; 16th August 2019 at 17:50. Reason: added tags

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  2. #2
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    Re: Comparator gives wrong Output

    Since the question wants you to compare values for greater than the inputs x and y should not be single bits but should instead be a vector, so they can be more than just 1'b1 and 1'b0.

    If they are supposed to be 1-bit then the assignment z = ~y + x is wrong since adding won't tell you if x >= y

    It should be simply z = ~(~x & y); // result is 0 only if x < y, otherwise if x==y or x>y it is 1


    1 members found this post helpful.

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