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  1. #1
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    verilog code using vivado

    hello everyone..
    Iam trying to implement a simple code using Arty A7 kit. In this code iam converting a train of three pulse into a single pulse. I completed with the code ,simulation,implementation ,bit streaming . Now Iam getting error in clocking process .Some of the cells are not clocked properly. Please help me how to select clocking in vivado.Click image for larger version. 

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    Last edited by FvM; 16th August 2019 at 10:33. Reason: Moved to appropriate section

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    Re: verilog code using vivado

    The post body doesn't match the title. Where's the Verilog code?



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    Re: verilog code using vivado

    Post the complete RTL.
    Are you properly doing the system clock input pin assignment in the xdc file?
    FPGA enthusiast!



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  4. #4
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    Re: verilog code using vivado

    Something tells that they are using the input pulse signal as a clock and didn't define anything for it. Based on the name alone sig_in and the names of the registers being clocked.



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