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verilog code using vivado

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sumag

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hello everyone..
Iam trying to implement a simple code using Arty A7 kit. In this code iam converting a train of three pulse into a single pulse. I completed with the code ,simulation,implementation ,bit streaming . Now Iam getting error in clocking process .Some of the cells are not clocked properly. Please help me how to select clocking in vivado. Capturenw123.JPG
 
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The post body doesn't match the title. Where's the Verilog code?
 

Post the complete RTL.
Are you properly doing the system clock input pin assignment in the xdc file?
 

Something tells that they are using the input pulse signal as a clock and didn't define anything for it. Based on the name alone sig_in and the names of the registers being clocked.
 

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