rrucha
Member level 3
Hi,
I am making use of $urandom to insert an error in random bits of data. To begin with, I am inserting a 1 bit error, where the position bit is randomly chosen and flipped. I am new to SystemVerilog and I noticed that it only executes once. I give data to the module through my testbench, and I want it to iteratively add errors to the same data at different bit positions. I made use of repeat(50), but it does the final work only on the last data.
I am making use of $urandom to insert an error in random bits of data. To begin with, I am inserting a 1 bit error, where the position bit is randomly chosen and flipped. I am new to SystemVerilog and I noticed that it only executes once. I give data to the module through my testbench, and I want it to iteratively add errors to the same data at different bit positions. I made use of repeat(50), but it does the final work only on the last data.
Code:
module error_inject (data_in, parity_in, data_out, parity_out);
parameter DATA_WIDTH = 13;
parameter ERROR_WIDTH = $clog2(DATA_WIDTH);
input [7:0] data_in;
input [4:0] parity_in;
output reg [7:0] data_out;
output reg [4:0] parity_out;
reg [ERROR_WIDTH-1:0] BIT_to_flip;
reg [DATA_WIDTH-1:0] int_data;
always @(*)
repeat(50)
begin
int_data = {data_in, parity_in};
idx_to_flip = $urandom_range(0, DATA_WIDTH-1);
$display("Flipping data bit %d", BIT_to_flip);
int_data[BIT_to_flip] = !int_data[BIT_to_flip];
$display("bad data = %b",int_data);
data_out = int_data[12:5];
parity_out = int_data[4:0];
end
endmodule