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    Protocol Design - System Verilog

    Hello, I am designing a protocol as a part of my project. I did the interface part and now I am asked to do the CSR coding for master and slave separately. I donít know where to start with. Can anyone explain what CSR is and how it works for master and slave so that I can move forward with my project?

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    Re: Protocol Design - System Verilog

    In my experience people use CSR when they are referring to the Control and Status Registers. But then again it might mean something else, which is why I avoid using acronyms unless they are very standardized across all disciplines.



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    Re: Protocol Design - System Verilog

    Quote Originally Posted by ads-ee View Post
    In my experience people use CSR when they are referring to the Control and Status Registers. But then again it might mean something else, which is why I avoid using acronyms unless they are very standardized across all disciplines.
    Yes, Iím supposed design this Control and Status Register. But I donít knwo how it will differ for the master and slave part. The protocol I am designing is OCP. I did the interface part. But I donít know how to do this CSR part.



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    Re: Protocol Design - System Verilog

    Once again an acronym...I have no clue what OCP means. Google reports it stands for...

    Oregon Catholic Press
    Open Compute Project
    Oracle Certified Professional
    ...

    See it's bad to use any acronyms unless you are only discussing with people on your acronym soup project.



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    Re: Protocol Design - System Verilog

    OCP was abbreviated as in VLSI Open Core Protocol.



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    Re: Protocol Design - System Verilog

    Quote Originally Posted by SOMISETTYRAKESH View Post
    OCP was abbreviated as in VLSI Open Core Protocol.
    OCP, as far as my impression of the industry goes, is a dead technology. Maybe OP could try AXI, SPI, etc.
    Really, I am not Sam.



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