Pastel
Member level 3
Hello!
As explained in another post, I'm trying to make a multichannel signal generator.
At the moment, it works fine with sine waves, which is quite boring, but at least
it works. The previous problems were how to use the on-chip RAM, and thanks to your
help, I could use it, it was a matter of setting the right option.
Now I have 2 signals, but I want more (about 8). In this case, I have to instantiate
4 ROMs, but I found no other solution than using the same module 4 times, and the
problem is that it loads the same data. Although it's not the case, if I want to make
a 8 channel sine wave, it's quite silly to store the same data at 4 different places.
What would be the right strategy to continue?
I was thinking about :
1. Storing only 1/4 of the wave in every dual port ROM instance. So it would save
3/4 of the space, so if I use 4, it's stil silly because I store 4 times the quarter
wave, but at least it saves space. BUT: in this case I can't use the on chip RAM because
it expects the data to be thrown unconditionally, and I just made a test by unfolding
the quarter sine wave. I tried, it works, it makes a sine wave from a quarter of a
sine wave, but no internal RAM is used, RAM Can't be used, apparenlty.
2. Storing the wave to user flash.
I don't know how to do that, but before trying it, I would like to know if I can
access it as fast as the RAM (i.e. at 50MSpl/s). If I can, then it would be an option.
Question: would the flash be fast enough to throw samples at 50Msps?
3. Storing a full sinewave (which therefore enables to use the RAM), but with less
samples. For instance 1024. Then with an interpolation by a power of 2 (very fast),
I should be able to get the job done fast enough.
Question: can an interpolation be done at every cycle?
For example if I interpolate by N (which is a power of 2), I would use an accumulator
acc with N more bits than my data. Then a sample between data and data[i+1] at a istance
k from data (0 < k < N), then I would calculate acc <= k * data + (N-k) data[i+1]
and then finally DA <= acc[WID+N-1:N].
Does this make sense?
Any hint or comment? Another strategy?
Pastel
As explained in another post, I'm trying to make a multichannel signal generator.
At the moment, it works fine with sine waves, which is quite boring, but at least
it works. The previous problems were how to use the on-chip RAM, and thanks to your
help, I could use it, it was a matter of setting the right option.
Now I have 2 signals, but I want more (about 8). In this case, I have to instantiate
4 ROMs, but I found no other solution than using the same module 4 times, and the
problem is that it loads the same data. Although it's not the case, if I want to make
a 8 channel sine wave, it's quite silly to store the same data at 4 different places.
What would be the right strategy to continue?
I was thinking about :
1. Storing only 1/4 of the wave in every dual port ROM instance. So it would save
3/4 of the space, so if I use 4, it's stil silly because I store 4 times the quarter
wave, but at least it saves space. BUT: in this case I can't use the on chip RAM because
it expects the data to be thrown unconditionally, and I just made a test by unfolding
the quarter sine wave. I tried, it works, it makes a sine wave from a quarter of a
sine wave, but no internal RAM is used, RAM Can't be used, apparenlty.
// ROM must be read unconditionally to infer dual port ROM
2. Storing the wave to user flash.
I don't know how to do that, but before trying it, I would like to know if I can
access it as fast as the RAM (i.e. at 50MSpl/s). If I can, then it would be an option.
Question: would the flash be fast enough to throw samples at 50Msps?
3. Storing a full sinewave (which therefore enables to use the RAM), but with less
samples. For instance 1024. Then with an interpolation by a power of 2 (very fast),
I should be able to get the job done fast enough.
Question: can an interpolation be done at every cycle?
For example if I interpolate by N (which is a power of 2), I would use an accumulator
acc with N more bits than my data. Then a sample between data and data[i+1] at a istance
k from data (0 < k < N), then I would calculate acc <= k * data + (N-k) data[i+1]
and then finally DA <= acc[WID+N-1:N].
Does this make sense?
Any hint or comment? Another strategy?
Pastel