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Using VCVS as delay elements result in period signal rising and falling time changing

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xianweng

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Hi, everyone,

My cadence version is IC6.1.7 and MMSIM version is 13.1. I am using VCVS as delay unit (I know there are some delay component in analogLib like delayline, but there are some other strange phenomena).

The testbench and simulation results are shown in the following figures. The gain of vcvs is 1 and delay time is 1.1us. The vpulse period is 7ms, pulse width is 800ns as shown in fig2. The result of the first period is right as shown in fig3, but the second period result is wrong as shown in fig4. The rising and falling time of fig4 are 177ns, which changed significantly. And the fourth period is right.
6136.testbench.jpg-320x240.jpg
fig1. Testbench
vsource.jpg-320x240.jpg
fig2. configuration of vpulse
sim1.jpg-320x240.jpg
fig3. The simulation of the first period
sim2.jpg-320x240.jpg
fig4. The simulation of the second period

Any hint on that?

Best regards,

xianweng
 

Have you tried changing the maxstep parameter in your transient simulation?
 

I've never used the Cadence analogLib vcvs in this way.
Are there perhaps other non-displayed params that set
tr/tf (or slew rate)?
 

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