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always_comb error in SystemVerilog code with case statement

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rrucha

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I am getting an error in this alway_comb block which uses case statement. I cant understand what is going wrong.

here is the block
Code: 
  always_comb
  begin 
    
   case (vxh[3:0])
    4'd0 : x = {{12{1'b0}}, 1'b1};
    4'd1 : x = {{11{1'b0}}, 1'b1, {1{1'b0}}};
    4'd2 : x = {{10{1'b0}}, 1'b1, {2{1'b0}}};
    4'd3 : x = {{7{1'b0}}, 1'b1, {5{1'b0}}};
    4'd4 : x = {{9{1'b0}}, 1'b1, {3{1'b0}}};
    4'd5 : x = {{6{1'b0}}, 1'b1, {6{1'b0}}};
    4'd6 : x = {{5{1'b0}}, 1'b1, {7{1'b0}}};
    4'd7 : x = {{4{1'b0}}, 1'b1, {8{1'b0}}};
    4'd8 : x = {{8{1'b0}}, 1'b1, {4{1'b0}}};
    4'd9 : x = {{3{1'b0}}, 1'b1, {9{1'b0}}};
    4'd10 : x = {{2{1'b0}}, 1'b1, {10{1'b0}}};
    4'd11 : x = {{1{1'b0}}, 1'b1, {11{1'b0}}};
    4'd12 : x = {1'b1, {12{1'b0}}};
  	default : x = {{11{1'b0}}, 2'b1};
	
   endcase
  end
 

Who writes cryptic code like this!? It almost looks like someone is trying to write obfuscated Systemverilog.

Code: 
4'd0 : x = 13'b 0_0000_0000_0001;
4'd1 : x = 13'b 0_0000_0000_0010;
..
is way easier to see what is going on.

Once again you don't provide any details about what your error message is.

Provide your error message, edaboard users are not clairvoyant.

If I have to guess you're compiling without Systemverilog enabled, so it doesn't like the always_comb (which is a Systemverilog keyword).
 

ads-ee said:
Who writes cryptic code like this!? It almost looks like someone is trying to write obfuscated Systemverilog.

Code: 
4'd0 : x = 13'b 0_0000_0000_0001;
4'd1 : x = 13'b 0_0000_0000_0010;
..
is way easier to see what is going on.

Once again you don't provide any details about what your error message is.

Provide your error message, edaboard users are not clairvoyant.

If I have to guess you're compiling without Systemverilog enabled, so it doesn't like the always_comb (which is a Systemverilog keyword).
Click to expand...

I am obviously not that stupid to run a SystmeVerilog code in a compiler that does not support SystemVerilog. And neither can I provide the entire code as it wont be necessary; the error is in this part of the code. i am using Synopsis VCS. I get an error which points out the line of "case (vxh[3:0])"
It only says there is an error in the line. I tried two different tools that support SystemVerilog. The error is shown in the same line.
It is a SECDED decoder coder.

Thanks
 

rrucha said:
I am obviously not that stupid to run a SystmeVerilog code in a compiler that does not support SystemVerilog. And neither can I provide the entire code as it wont be necessary; the error is in this part of the code. i am using Synopsis VCS. I get an error which points out the line of "case (vxh[3:0])"
It only says there is an error in the line. I tried two different tools that support SystemVerilog. The error is shown in the same line.
It is a SECDED decoder coder.

Thanks
Click to expand...

So you know it's in this code, right? You are absolutely sure of it....

Well try using your tools on this file, which I already tested with Modelsim and Vivado's simulator, though I didn't bother wasting my time synthesizing the file as I already know the case statement was fine as written.
Code: 
module case_test (
  input  logic [3:0]  vxh,
  output logic [12:0] x

);


  always_comb
  begin 
    
   case (vxh[3:0])
    4'd0 : x = {{12{1'b0}}, 1'b1};
    4'd1 : x = {{11{1'b0}}, 1'b1, {1{1'b0}}};
    4'd2 : x = {{10{1'b0}}, 1'b1, {2{1'b0}}};
    4'd3 : x = {{7{1'b0}}, 1'b1, {5{1'b0}}};
    4'd4 : x = {{9{1'b0}}, 1'b1, {3{1'b0}}};
    4'd5 : x = {{6{1'b0}}, 1'b1, {6{1'b0}}};
    4'd6 : x = {{5{1'b0}}, 1'b1, {7{1'b0}}};
    4'd7 : x = {{4{1'b0}}, 1'b1, {8{1'b0}}};
    4'd8 : x = {{8{1'b0}}, 1'b1, {4{1'b0}}};
    4'd9 : x = {{3{1'b0}}, 1'b1, {9{1'b0}}};
    4'd10 : x = {{2{1'b0}}, 1'b1, {10{1'b0}}};
    4'd11 : x = {{1{1'b0}}, 1'b1, {11{1'b0}}};
    4'd12 : x = {1'b1, {12{1'b0}}};
  	default : x = {{11{1'b0}}, 2'b1};
	
   endcase
  end

endmodule

This is why I asked what the exact error message was. The problem is obviously somewhere else in the code like you defined the vxh incorrectly (probably as an integer or similar nonsense) or you've got a problem in some previous section of code and the problem doesn't show up until it reaches the case statement (unlikely due to the always_comb).

rrucha said:
I am obviously not that stupid to run a SystmeVerilog code in a compiler that does not support SystemVerilog.
Click to expand...
Never suggested you were "stupid", as the posted code was valid the only possible problem based on the minimal information given was due to attempting to compile a Systemverilog file as Verilog. Context is important, showing snippets of perfectly valid code and claiming it has a problem isn't useful. Showing all the code or at least the code that defines everything is mandatory if you want help and not suggestions that you compiled without systemverilog enabled. Won't bother to count the number of times the problems with a poster's code is in the way the defined something and isn't in the snippet they posted.

- - - Updated - - -

Just thought of another possibility...

How about a non-printable character inserted in the file. I've seen this happen on a couple of occasions where some non-printable character gets inserted by some garbage editor that simulator and synthesis tools then barf on. Just retyping a block of code and deleting the old one fixed the problem. You can check for this if you have an editor that can convert to hex and back or one that allows you to display everything.
 

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