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  1. #1
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    Injecting errors in SystemVerilog

    I have an error detection code which has a generator and a receiver. The receiver checks if there were any errors while transmission. I have a testbench, where I plan to add an error injecting mechanism. I want to add errors at random places. Is there a specific way to do it?

    I was thinking of making a module in the test bench that will flip one random bit in the data that is received. Is this the right way to implement random error injection in SystemVerilog? If not, how else can I do it?

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  2. #2
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    Re: Injecting errors in SystemVerilog

    Well, I don't know if it is Systemverilog-ish or not but I used a $random_range to generate a error word, and xor'd it with the data that was passed through the EDAC so I could verify the EDAC circuit I built. Did this with both checking single, and double bit errors.



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  3. #3
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    Re: Injecting errors in SystemVerilog

    depends on the application. for something like hamming code with reasonable bus widths you can just have a N**2 loop where data = data ^ ((1<<i) | (1<<j)). and i,j can be one higher than the bus width with ecc. Simple to write, not efficient, but doesn't really matter for hamming codes.

    you can do this with random functions or counters or such to determine the error locations.



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