Hi guys,
Following figure shows the characteristic of a linear PD [1], What will happened if the phase of the clock is between 0ps~10ps or 90ps~100ps?
Papers and textbooks seldom discussed about it in that situation.

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[1] J. Savoj and B. Razavi, "Design of half-rate clock and data recovery circuits for optical communication systems," Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232), Las Vegas, NV, USA, 2001, pp. 121-126.
doi: 10.1145/378239.378366