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  1. #1
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    How to compare variables name

    I would like to check if the name of two variables is the same.

    In particular one of those variable is the input of a task and the other one is a variable declared in the main.
    Code:
    module ex();
         logic        clk;
         logic [ 3:0] btn;
         logic        vaux2_p;
         logic        vaux2_n;
         logic        gpio1;
         logic        gpio2;
    
      main dut(
        .clk(clk),
        .btn (btn),
        .vaux2_p (vaux2_p),
        .vaux2_n (vaux2_n),
        .pio3 (pio3),
        .pio4 (pio4)
        );
    
    task test;
        input [ 7:0] a;
        input [23:0] v;
        input [23:0] s;
        integer f1;
        integer f2;
          begin
                f1 = $fopen("file.txt","w");
                 if (!f1) begin
                   $display("File \"file.txt\" cannot be opened!");
                 end else begin
                      if(s=="dut.f") begin
                            $fwrite(f1, "1:\n");
                      end else if(s=="dut.f") begin
                            $fwrite(f1, "2:\n");
                      end
                 end
    endtask
    
      initial begin
        test(8'h1a,16'hF0, dut.f);
    
        $finish;
      end
    endmodule
    I already know that there is an error in my code due to the fact that I'm comparing the value of s with the name of dut.f, but I don't know how to compare the names. Can anyone help me please? Thanks!

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  2. #2
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    Re: How to compare variables name

    ASCII strings would be represented by string type, not bit vectors. There's however no direct access to object names. You may check if vpi_handle_by_name() serves your purposes.



  3. #3
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    Re: How to compare variables name

    Thanks for your reply, but it seems that vpi_handle_by_name() won't be useful in my case. Anyway I menage to compare the variables name in a different way. Thank you!



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  4. #4
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    Re: How to compare variables name

    many years ago, some compilers/??? would list all variables and what line they were on, in a program
    it did not take into account subroutines and scope
    perhaps your system has that capability



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    Re: How to compare variables name

    No I don't think my system has that capability, but using strings it has been possible to compare two variable names.



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    Re: How to compare variables name

    #2 I've noticed vpi handle in the vhdl standard? What is this?

    Is this the way the software processes the rtl code.

    Can you talk to modelsim/questasim or whatever software using these functions?



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  7. #7
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    Re: How to compare variables name

    Quote Originally Posted by wesleytaylor View Post
    #2 I've noticed vpi handle in the vhdl standard? What is this?

    Is this the way the software processes the rtl code.

    Can you talk to modelsim/questasim or whatever software using these functions?
    VPI is from verilog https://en.wikipedia.org/wiki/Verilo...ural_Interface though apparently it has been partially ported to VHDL as VHPI. I only saw a link for GHDL having support, don't know if any other simulators support it.

    Mainstream Verilog/Systemverilog simulators support VPI and it's predecessor PLI, it's a way to access the database that the simulator creates directly with the C programming language.


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