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26th July 2019, 08:39 #1
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How to measure the input reactance and output reactance of a MOSFET/gain stage
Hi, I found relative answers to the question but I want a little clarity.
https://www.edaboard.com/showthread....ceofaMOSFET
https://www.edaboard.com/showthread....nputimpedance
https://www.edaboard.com/showthread....ncecalculator
https://www.edaboard.com/showthread....or(SpectreRF)
I mentioned it as reactance as a general case but I know it is mostly capacitance. How do I find input/output capacitance of a gain stage/MOSFET/Network?. Usually it is the imaginary part of the total input/output impedance. So If I do SP simulation and plot the imaginary part of ZP from direct plot, It will give me the input/output capacitance of a gain stage. Correct? But why do some people use YP from direct plot for this purpose. I just want to know which parameter to use (Say ZP) and what modifications I should make if I use the other parameters(Say YP).
P.S I know if the network has series connection it is easier to use Z parameters and If it is parallel connections it is easier to use Y parameters. But If we consider the network as a block box we wouldn't know how the connections are inside.

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26th July 2019, 15:22 #2
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Re: How to measure the input reactance and output reactance of a MOSFET/gain stage
You should not use Sparameters, since you can not understand RF.
Open state.
Short state.
Consider a definition of Z11 and Y11.
Surely learn a definition of Z and Y parameters.
It is very easy linear algebra whatever you use as 2port parameters.Last edited by pancho_hideboo; 26th July 2019 at 15:51.

27th July 2019, 07:42 #3
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Re: How to measure the input reactance and output reactance of a MOSFET/gain stage
No.. If you are interested in the input impedance, look at ZM1 and for output impedance, look at ZM2. Not Z parameters. V1 = Z11*I1 + Z12*I2. If you only look at Z11, then you don't see the effect of Z12 which is the effect of the feedforward capacitance (aka Cgd). ZM1 captures both of them.

27th July 2019, 09:20 #4
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Re: How to measure the input reactance and output reactance of a MOSFET/gain stage
Hi,
In my eyes the miller effect makes the system unlinear, you see this in the voltage plateau of V_gs.
Thus you can't apply S parameters.
You need to input power to get the gate charged. ... but you don't get the whole power back, because all the power for the miller effect is dissipated within the Mosfet.
It is a lossy unlinear system, depending on V_DS...and can't be simulated with an R C circuit.
KlausPlease don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.

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27th July 2019, 11:31 #5
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Re: How to measure the input reactance and output reactance of a MOSFET/gain stage
Yeah sure.
I used this
1.CinfromY=(1 / (abs(imag((1 / ypm('sp 1 1)))) * 6.28 * xval(ypm('sp 1 1))))
2.Cin=(abs(imag(zm(1 ?result "sp"))) / (2 * 3.14 * xval(zm(1 ?result "sp"))))
There is a lot of difference between two of the results and using 2. the Cin value is not constant over the frequency range. That is the my confusion as to which one to use and the Cgd effect would so much ?

27th July 2019, 16:38 #6
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Re: How to measure the input reactance and output reactance of a MOSFET/gain stage
The expression for Cin is incorrect.
Xc = abs(1/imag(1/zm(1 ?result "sp")) )
Cin = 1 / (Xc*(2*3.14159*xval(zm(1 ?result "sp"))))
Xc = 1/jwC ==> C = 1/(j*w*Xc)
This Cin is Cgs + Av*Cgd
You can check this value at very low frequencies. Your Cin is in nF which is really high.

27th July 2019, 17:01 #7
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Re: How to measure the input reactance and output reactance of a MOSFET/gain stage
Are you truely sure ?
Very wrong. Can you understand imag(1/admittance) ?
Very wrong. Can you understand imag(impedance) ?
It is a very natural result.
It is a very natural result.
Both are very very very very wrong.
Simply you can not understand impedance and admittance at all.
Surely learn a definition of Z and Y parameters.
Y11 is a short state admittance.
Z11 is a open state impedance
ZM1 is a loaded impedance where load impedance value is reference impedance.
Wrong.
Z11 surely includes the effect of Cgd due to intrinsic load.
I don't think Yin=1/zm(1 ?result "sp") is not appropriate, since circuitslave can not understand Sparameters at all.
I don't think reference impedance is matched to actual load resistance.
Show me reference impedance and load impedance.Last edited by pancho_hideboo; 27th July 2019 at 17:18.

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27th July 2019, 17:26 #8
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Re: How to measure the input reactance and output reactance of a MOSFET/gain stage
Z11 surely includes the effect of Cgd due to intrinsic load.

31st August 2019, 12:25 #9
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