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mosfet as a switch in 28nm technology

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aka_rabbi

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Hello, everyone.
I want to know the proper way to use a single mosfet as a switch in the nano scale from anybody who has experience in design.
I know that Vgs will turn the mosfet on or off.

How do the L and W affect the device as a switch?
what are the proper layout technique for switch?
in simulation do you look at the Ids? or any other parameter to verify if it is functioning properly?
does nmos work better as a switch?
 

Hello, everyone.
I want to know the proper way to use a single mosfet as a switch in the nano scale from anybody who has experience in design.
I know that Vgs will turn the mosfet on or off.

How do the L and W affect the device as a switch?
If you increase W, you decrease the resistance of the switch. If you increase L, then you increase resistance but at the same time decrease leakage in the off state. Also increasing length impacts the Vth in nano CMOS.
what are the proper layout technique for switch?
Try and reduce all parasitic feedthrough capacitances.

in simulation do you look at the Ids? or any other parameter to verify if it is functioning properly?
I connect one end to the maximum source voltage, the other end to maximum input source voltage + 1 mV and see the resistance by measuring DC current. For me all the applications I worked on required DC resistance < 5 ohms and currents < 1mA. So, the overall drop would be 5mV which is close enough for me. But in case you have a larger current, a better design strategy would be connect one end to the maximum input source voltage, the other end to the maximum input source voltage + the maximum drop across the switch that you can tolerate. Then connect the gate to the Vdd and sweep the W/L until you get the value of drain current you want. (Don't be stingy. Put some margin on the current).
does nmos work better as a switch?
Depends! If your maximum input source voltage is close to VSS, then nmos would be a better choice as you maximize Vgs. If your maximum input source voltage is close to Vdd, then you are better off using a PMOS. The mobility difference between PMOS and NMOS is not much in nano-scale CMOS, especially at 28GHz.
 
thank you so much. Can you recommend a book that teaches layout from the EDA tool perspective(like how a designer would approach)?
 

Sorry, but I am not personally aware of any such book. Every design has its own challenges and only designing blocks can help you understand the tradeoffs
 

Are you asking about a book on layout in general, or on power transistor layout?
 

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