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Voltage sharing for IGBT's in series

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Swend

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Hi friends.

I read and simulated the following application note https://www.ixys.com/Documents/AppNotes/IXAN0057.pdf

What I can't understand is why it takes long time (300nS) for the current in the load to peak AFTER the IGBT's are turned ON?

Screenshot from 2019-07-22 21-54-31.png
 

generally IGBT's can turn on very fast, if driven hard, i.e. Vgate rise <30nS, in your case you have emitter degeneration with the emitter inductance, a rising current in this inductance provides a counter EMF which subtracts from the gate drive voltage, V = L.di/dt

Also, at turn on, you have the snubber caps discharging into the devices, raising the current & the di/dt in the emitter inductance.

Also, as the collector volts fall, it tends to pull the gate down with it via Ccg again slowing turn on

thus the device is held in a kind of linear state, limiting the di/dt while the current in increasing towards the load current ...

Probing Vemitter and subtracting from Vgate external will give you a better look at what is going on in terms of real gate drive

probe the current in each device - and the snubber cap current too, to get a more complete, self explanatory picture.
 

Hi Easy peasy,

Thnk you for the explanation. I can see that it must be in a kind of linear state created by the inductance, but I don't see the connection to the Vg, as you can see in the top trace plane I did exactly what you said i.e. probing Vemitter and subtracting from Vgate, and the gate signal is squeaky clean.

The snubber caps as you call them, are meant to act as an dynamic voltage divider ref. application note. I did also measure the current in those as that would be my next question, why are the cap currents so high? They are close to 250A? And secondly what effect would that have on the circuit as a whole? I mean does it make the circuit highly inefficient?

Screenshot from 2019-07-23 10-30-43.png
 

you have not plotted Vgate-Vemitter. Looking at Vgate alone is meaningless. You ask why the cap currents are so high - can you not see the IGBT is shorting them at turn on? this also contributes to Vemitter rise at turn on - as I said above ....
 

you have not plotted Vgate-Vemitter. Looking at Vgate alone is meaningless. You ask why the cap currents are so high - can you not see the IGBT is shorting them at turn on? this also contributes to Vemitter rise at turn on - as I said above ....

I'm pretty sure I did plot Vgate-Vemitter or maybe I just don't understand what you mean in which case please rephrase. If you look in the top trace plane there are two traces V(Td2-gate) and V(Td1-gate)-V(mid1). V(Td2-gate) is plotted with GND as reference because it's emitter is connected to GND. And V(Td1-gate)-V(mid1) is the Vgate-Vemitter because the net "mid1" is connected to the emitter of Td1?

yes I can see the IGBT is shorting the caps at turn on, I'm just wondering why their di/dt is much higher and non-linear in contrast to Rload who is also connected to the IGBT's?
 

look on your schematic where it says "G" and again where it says "E" plot (Ve-Vg) this is the true gate voltage ...

their di/dt is higher because they can reach a much higher I - i.e not limited by 30 ohms ...
 
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    Swend

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look on your schematic where it says "G" and again where it says "E" plot (Ve-Vg) this is the true gate voltage ...


ahhhh, but you see the igbt model I'm using did not include the intrinsic/parsitic GCE inductances, however in the model file there were instructions how to add the correct inductances - which I did, and those are the three inductors connected directly to the GCE of each IGBT..

their di/dt is higher because they can reach a much higher I - i.e not limited by 30 ohms ...

Obviously, I didn't see that, thank you.
 

sorry, plot VG-VE then you will see a reduced gate drive due to lead inductance effects and Ccg ...
 

sorry, plot VG-VE then you will see a reduced gate drive due to lead inductance effects and Ccg ...

Like this?
Screenshot from 2019-07-23 13-38-17.png

I don't know how interpret that, to me it's more like measuring inside the igbt i.e. something you can't do anything about.
 

Emitter degeneration was also my guess, but in the present simulation, the effect of parasitic inductances is relatively small due to the moderate gate voltage rise time.

I don't understand however the purpose of the simulation related to your work. It's all about dealing with huge gate driver skew, in the present example 100 ns. If you don't have it, you don't need large dynamic voltage sharing capacitors and thus don't experience high discharge currents.
 

Emitter degeneration was also my guess, but in the present simulation, the effect of parasitic inductances is relatively small due to the moderate gate voltage rise time.

I don't understand however the purpose of the simulation related to your work. It's all about dealing with huge gate driver skew, in the present example 100 ns. If you don't have it, you don't need large dynamic voltage sharing capacitors and thus don't experience high discharge currents.

I wouldn't have though so too until I took four of my IGBT's and connected them in series without voltage sharing and ~0% driver skew, with the net result that all four blew up. Then I concluded that what I needed was voltage sharing, but my conclusion may be wrong.
 

Voltage sharing means may be necessary, depending on the application. The 100 ns delay skew assumed in the simulation is unrealistically large for modern gate driver circuits.
 
Voltage sharing means may be necessary, depending on the application. The 100 ns delay skew assumed in the simulation is unrealistically large for modern gate driver circuits.

Yeah I know, I made the simulation just to confirm that the voltage sharing worked as intended because I have read a couple of papers dissing passive voltage sharing.

Anyway with four stages and 4KV input the efficiency is a tolerable 80%.
 

Voltage sharing can be accomplished with RC snubbers and volt sharing R's ( for DC )

your sim shows 40V on the gate ( internal to the device ) when the IGBT starts to conduct the cap current - this also may kill devices

better to add zener/TVS across each IGBT in practice for extra protection

Your IGBT model is likely a little on the simple side to fully reflect the dynamics of what is occurring on the true gate capacitance

Better to build and test and gradually raise the HVDC until things start to go wrong, then add snubbers etc to correct and test at increasing voltages...

- - - Updated - - -

p.s. transformer gate drive is the best way to go - else the dv/dt at turn on can affect other methods, via device capacitance.
 

The PCB's arrived and I populated 8 modules and call that a 'stack'

They are connected (+V)(E-C).......(E-C)(0V)

**broken link removed**

First I tried with four modules in series, voltage sharing works - then I turn the IGBT's ON for 500uS and it still works. HOWEVER.... I can not increase supply voltage above 3KV, none of the supplies I tried (NST,OBIT,FB all 20-40mA) could do it, they all stopped at 3KV regardless of how much I cranked the voltage up. The current through the stack is around 1mA with the IGBT's OFF.

Then I thought, let me try with eight modules in the stack, same problem supply stopped at 3KV and then something gave up in the stack while messing with the voltage knob, five IGBT's blew up, the ones closest to the supply (+V).

This is getting very frustrating now. I suspected the 0.47nF caps because they are cheap chinese caps, I soldered them out, but no change, then soldered them back. The rest of the components are original stock from reputed distributors.

I don't know where to go from here, so suggestions are very welcome.
 

almost impossible to help without a clear schematic ...

- - - Updated - - -

leakage currents are most likely getting to the gates above 3kV just enough to start current thru the IGBT's ...
 

almost impossible to help without a clear schematic ...

- - - Updated - - -

leakage currents are most likely getting to the gates above 3kV just enough to start current thru the IGBT's ...

I see my attachment is showing an error in post 15, so here it is again

single-igbt-module.png

It's really noting more that eight of these and a power supply.
 

you really need a small fet or pnp holding the gate down when IGBT should be off.
 

I can not increase supply voltage above 3KV, none of the supplies I tried (NST,OBIT,FB all 20-40mA) could do it, they all stopped at 3KV regardless of how much I cranked the voltage up.
Can you convince us that the circuit including gate driver and driver supply has sufficient insulation strength for 3 kV? The Infineon driver is e.g. specified with +/-1200V only.
 

how are you isolating all the gate drivers?

data sheet say 25uA leakage C-E so 1 meg-ohm ( 2W ) should give OK static volt sharing, I note the 470pF cap is it 2kV rated?

- - - Updated - - -

that driver IC is only good for 1 stage, 1200V, above 3kV the internal transformer breaks down ( read the data sheet )

so for more than one stage you need well isolated xfmrs to propagate the gate drive signal ...
 

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