+ Post New Thread
Results 1 to 6 of 6
  1. #1
    Full Member level 3
    Points: 1,014, Level: 7

    Join Date
    Jan 2018
    Posts
    160
    Helped
    1 / 1
    Points
    1,014
    Level
    7

    What's the difference between stacked and cascode configurations?

    Hi This question already being answered here but I want some clarifications.
    https://www.edaboard.com/showthread....cked+amplifier


    Millimeter-Wave Power Amplifiers by Jaco du Preez, Saurabh Sinha
    Click image for larger version. 

Name:	stack_amplifier.JPG 
Views:	5 
Size:	22.7 KB 
ID:	154517

    In the figure, if I don't connect the capacitors (Cn) at the gate terminals then it becomes cascode and if I connect capacitors then it is stacked configurations. is that it?

    "The bottom device is configured in a common source mode, while the remainder
    of the transistors are operated without grounding any particular terminal in a
    common-gate-like setup. "

    1.If I imagine the small signal model, the gate teminals will definately be grounded because capacitor is short for AC and VGNs are connected to ground. I don't understand what they mean by that.

    "The configuration shown in Fig differs from a cascode amplifier where the common-gate transistor is grounded at the center
    frequency. In a stacked design, the gate terminal of the common-gate-like device is
    connected to some finite impedance and the drain voltages are added in phase in an
    ideal situation"

    2.They say some finite impedance, does it mean it can be anything not just capacitance (like resistance, inductance or complex).

    3.In the FIgure, it is written Ropt, why does it need to be just resistance, it can be anything right? (I was thinking that I would get that Ropt from loadpull and ignore the imaginary part )
    Last edited by circuitking; 20th July 2019 at 21:54.

    •   AltAdvertisement

        
       

  2. #2
    Advanced Member level 5
    Points: 39,379, Level: 48

    Join Date
    Mar 2008
    Location
    USA
    Posts
    6,364
    Helped
    1855 / 1855
    Points
    39,379
    Level
    48

    Re: What's the difference between stacked and cascode configurations?

    I would call this figure a double-cascode, one FET is actively
    driven and the others have static gate bias.

    If you look at RF CMOS switches, those are stacked and all
    of the gates are co-driven "on" or "off".

    Don't overthink the "difference", there may be none except
    idiom.



    •   AltAdvertisement

        
       

  3. #3
    Super Moderator
    Points: 258,558, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    45,138
    Helped
    13723 / 13723
    Points
    258,558
    Level
    100

    Re: What's the difference between stacked and cascode configurations?

    In the figure, if I don't connect the capacitors (Cn) at the gate terminals then it becomes cascode and if I connect capacitors then it is stacked configurations. is that it?
    No. In the previous thread, it's just the other way round.

    Quite clearly, usual cascode configuration has the second (or possibly third) stage in CG, gate grounded. Apparently the author refers to stacked as a configuration where the second gate is also actively driven. Like dick_freebird, I'm not sure if this is commonly agreed terminology.



    •   AltAdvertisement

        
       

  4. #4
    Full Member level 3
    Points: 1,014, Level: 7

    Join Date
    Jan 2018
    Posts
    160
    Helped
    1 / 1
    Points
    1,014
    Level
    7

    Re: What's the difference between stacked and cascode configurations?

    Quote Originally Posted by FvM View Post
    No. In the previous thread, it's just the other way round.

    Quite clearly, usual cascode configuration has the second (or possibly third) stage in CG, gate grounded.
    What do you mean by gate grounded exactly?
    Quote Originally Posted by FvM View Post
    Apparently the author refers to stacked as a configuration where the second gate is also actively driven.
    Do you mean we can give input to the second gate also? But it doesn't show like that in the figure.

    Can I also say cascode configuration is also a stacked configuration with N=2? Then I will not have any confusion.



  5. #5
    Full Member level 3
    Points: 1,131, Level: 7

    Join Date
    Jan 2019
    Location
    Belgium
    Posts
    163
    Helped
    69 / 69
    Points
    1,131
    Level
    7

    Re: What's the difference between stacked and cascode configurations?

    Quote Originally Posted by circuitking View Post


    In the figure, if I don't connect the capacitors (Cn) at the gate terminals then it becomes cascode and if I connect capacitors then it is stacked configurations. is that it?
    This is cascode nevertheless. The capacitor does not serve any purpose here.

    See the following figure.

    Click image for larger version. 

Name:	cascode_vs_stacked.png 
Views:	5 
Size:	29.3 KB 
ID:	154529

    In cascode, C_CAS >> C_GS and therefore the gate is a virtual ground (Rb in combination with C_CAS forms a low pass filter) The look in impedance is 1/gm

    In stacked, the C_ST is of the same order as C_GS and the look in impedance can be written as (approximately) (1/gm)*(1+ C_GS/C_ST). Because the input impedance is no longer low, the swing in the source will be larger. This reduces the drain to source swing of the cascode transistor.
    By the way, the price you pay for going for a stacked configuration is that the gain is not as high as cascode.

    - - - Updated - - -

    Quote Originally Posted by circuitking View Post

    3.In the FIgure, it is written Ropt, why does it need to be just resistance, it can be anything right? (I was thinking that I would get that Ropt from loadpull and ignore the imaginary part )
    Yes it can be anything. Typically people place a matching network between a common source and common gate device.



    •   AltAdvertisement

        
       

  6. #6
    Full Member level 3
    Points: 1,014, Level: 7

    Join Date
    Jan 2018
    Posts
    160
    Helped
    1 / 1
    Points
    1,014
    Level
    7

    Re: What's the difference between stacked and cascode configurations?

    Quote Originally Posted by vivekroy View Post

    Click image for larger version. 

Name:	cascode_vs_stacked.png 
Views:	5 
Size:	29.3 KB 
ID:	154529
    Nice Explanation.
    Quote Originally Posted by vivekroy View Post
    In stacked, the C_ST is of the same order as C_GS and the look in impedance can be written as (approximately) (1/gm)*(1+ C_GS/C_ST). Because the input impedance is no longer low, the swing in the source will be larger. This reduces the drain to source
    I never connected C_CAS in any of my cascode topologies till now. In Conclusion for stack configuration, I should make sure C_ST is of the same order as C_GS.



--[[ ]]--