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Deep nwell connection

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vsupadhya

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Please help me with few questions related to deep nwell.

I have 3 inverters with 3 different power and ground. Power anyways will be isolated by nwell. To isolate 3 different grounds i need to use deep nwell. In this case can i use a single deep nwell for all 3 different grounds.?
 

Provided that you reverse bias the deep nwell to the highest of the three supplies, you can share the deep nwell. Just make sure you follow any violations/considerations implemented by the DRC rule deck/PDK. The three different grounds would each have their own ground biased pwells within the deep nwell. Make sure you have a lot of well contacts too.
 

In my opinion, it is better if you use 3 dnwell separately. To prevent noise from each pwell to others.
 

quyleanh said:
In my opinion, it is better if you use 3 dnwell separately. To prevent noise from each pwell to others.
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I agree. Unless you have hundreds of wells, you’re not going to save a lot of space by combining just three. There’s less risk with keeping them separate.
 

Why could he share the deep n well for the three different positive voltages? Wouldn't each of the inverter contact the deep n-well with their own n-well? Or is this feature technology dependand?
 

Deep nwell just provides a well to put p-implant. And the most important thing to consider is that the p well to dn well never forward biases. That is usually done by reverse biasing to the highest supply. The PMOS devices in the n-well usually are not in the deep nwell. If they are, then you’re right, you can’t connect them all together because they’ll create an ERC violation/short. The only time I’ve seen pmos devices in deep nwell is when they’re trying to increase the stand-off voltage. When I made my initial comment, I assumed only the NFETs would be in the deep nwell and you’d have a separate region for the pfets, there are standard cell guard rings in some PDKs that create this type of structure.
 

I have only worked with 2 technologies yet, but in both the deep n-wells were used isolate whole circuit blocks (at my current design even a square milimiter big block) from the substrate. For our optoelectronic designs the substrate will be biased to around -25V so any circuit needs to be isolated completly!
 

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